DF2372VFQ34V Renesas Electronics America, DF2372VFQ34V Datasheet - Page 575

• Manufacturer Part Number: DF2372VFQ34V
• Description: IC H8S/2372 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2372VFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.9
Port A is an 8-bit I/O port that also has other functions. The port A has the following registers.
• Port A data direction register (PADDR)
• Port A data register (PADR)
• Port A register (PORTA)
• Port A pull-up MOS control register (PAPCR)
• Port A open-drain control register (PAODR)
• Port function control register 1 (PFCR1)
10.9.1
The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be
read; if it is, an undefined value will be read.
Bit
7
6
5
4
3
2
1
0
Bit Name
PA7DDR
PA6DDR
PA5DDR
PA4DDR
PA3DDR
PA2DDR
PA1DDR
PA0DDR
Port A
Port A Data Direction Register (PADDR)
Initial Value
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Description
•
•
•
Modes 1 and 2
Pins PA4 to PA0 are address outputs regardless
of the PADDR settings.
For pins PA7 to PA5, when the corresponding bit
of A23E to A21E is set to 1, setting a PADDR bit
to 1 makes the corresponding port A pin an
address output, while clearing the bit to 0 makes
the pin an input port. Clearing one of bits A23E to
A21E to 0 makes the corresponding port A pin an
I/O port, and its function can be switched with
PADDR.
Modes 7 (when EXPE = 1) and 4
When the corresponding bit of A23E to A16E is
set to 1, setting a PADDR bit to 1 makes the
corresponding port A pin an address output,
while clearing the bit to 0 makes the pin an input
port. Clearing one of bits A23E to A16E to 0
makes the corresponding port A pin an I/O port,
and its function can be switched with PADDR.
Mode 7 (when EXPE = 0)
Port A is an I/O port, and its pin functions can be
switched with PADDR.
Rev.7.00 Mar. 18, 2009 page 507 of 1136
Section 10 I/O Ports
REJ09B0109-0700