MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 103

• Manufacturer Part Number: MCF5272VM66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, UART, Ethernet, SPI, USB, QSPI
• Maximum Clock Frequency: 166 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.4 V to 1.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 4
Local Memory
This chapter describes the MCF5272 implementation of the ColdFire Version 2 core local memory
specification. It consists of the following sections.
4.1
Depending on configuration information, instruction fetches and data read accesses may be sent
simultaneously to the SRAM, ROM, and cache controllers. This approach is required because the
controllers are memory-mapped devices and the hit/miss determination is made concurrently with the read
data access. Power dissipation can be minimized by configuring the ROM and SRAM base address
registers (ROMBAR and RAMBAR) to mask unused address spaces whenever possible.
If the access address is mapped into the region defined by the SRAM (and this region is not masked), it
provides the data back to the processor and any cache or ROM data is discarded. If the access address does
not hit the SRAM, but is mapped into the region defined by the ROM (and this region is not masked), the
ROM provides the data back to the processor and any cache data is discarded. Accesses from the SRAM
and ROM modules are never cached. The complete definition of the processor’s local bus priority scheme
for read references is as follows:
if (SRAM “hits”)
data
Freescale Semiconductor
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•
Section 4.3, “SRAM
RAM (SRAM) and ROM implementations. These chapters cover general operations,
configuration, and initialization. They also provide information and examples showing how to
minimize power consumption when using the ROM and SRAM.
Section 4.5, “Instruction Cache
organization, configuration, and coherency. It describes cache operations and how the cache
interfaces with other memory structures.
Interactions Between Local Memory Modules
SRAM supplies data to the processor
if (ROM “hits”)
MCF5272 ColdFire
Overview,” and
ROM supplies data to the processor
®
Overview,” describes the cache implementation, including
else if (cache “hits”)
Integrated Microprocessor User’s Manual, Rev. 3
Section 4.4, “ROM
cache supplies data to the processor
else system memory reference to access
Overview,” describe the on-chip static
4-1