MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 371
MCF5272VM66J
Manufacturer Part Number
MCF5272VM66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets
1.MCF5272CVF66J.pdf
(544 pages)
2.MCF5272CVF66J.pdf
(12 pages)
3.MCF5272VM66J.pdf
(44 pages)
Specifications of MCF5272VM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, UART, Ethernet, SPI, USB, QSPI
Maximum Clock Frequency
166 MHz
Number Of Timers
4
Operating Supply Voltage
1.4 V to 1.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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16.3.7
The transmitter buffers consist of a 24-byte FIFO and the transmitter shift register. The FIFO accepts
characters from the bus master if the channel’s USRn[TxRDY] is set. A write to the transmitter buffer
clears TxRDY, inhibiting any more characters until the FIFO can accept more data. When the shift register
is empty, it checks if the holding register has a valid character to be sent (TxRDY = 0). If there is a valid
character, the shift register loads it and sets USRn[TxRDY] again. Writes to the transmitter buffer have no
effect when the channel’s TxRDY = 0 and when the transmitter is disabled.
Figure 16-8
16.3.8
The input port change registers (UIPCRn),
CTS.
Table 16-7
Freescale Semiconductor
Bits
7–5
3–1
4
0
Address
Address
Reset
Name
Reset
COS
CTS
Field
Field
R/W
R/W
—
—
describes UIPCRn fields.
UART Transmitter Buffers (UTBn)
UART Input Port Change Registers (UIPCRn)
shows UTBn. TB contains the character in the transmitter buffer.
Reserved, should be cleared.
Change of state (high-to-low or low-to-high transition).
0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS].
1 A change-of-state longer than 25–50 μs occurred on the CTS input. UACRn can be programmed to generate
Reserved, should be cleared.
Current state. Starting two serial clock periods after reset, CTS reflects the state of CTS. If CTS is detected
asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled.
0 The current state of the CTS input is asserted.
1 The current state of the CTS input is negated.
an interrupt to the CPU when a change of state is detected.
7
7
MCF5272 ColdFire
Figure 16-9. UART Input Port Change Registers (UIPCRn)
—
Figure 16-8. UART Transmitter Buffers (UTBn)
Table 16-7. UIPCRn Field Descriptions
®
MBAR + 0x110 (UIPCR0), 0x150 (UIPCR1)
5
Integrated Microprocessor User’s Manual, Rev. 3
Figure
0000_011
MBAR + 0x10C,0x14C
COS
16-9, hold the current state and the change-of-state for
4
0000_0000
Write only
Read only
Description
TB
3
111
1
UART Modules
CTS
CTS
0
0
16-11
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