MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 239
MCF5272VM66J
Manufacturer Part Number
MCF5272VM66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets
1.MCF5272CVF66J.pdf
(544 pages)
2.MCF5272CVF66J.pdf
(12 pages)
3.MCF5272VM66J.pdf
(44 pages)
Specifications of MCF5272VM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, UART, Ethernet, SPI, USB, QSPI
Maximum Clock Frequency
166 MHz
Number Of Timers
4
Operating Supply Voltage
1.4 V to 1.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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11.5.11 Transmit FIFO Watermark (TFWR)
The TFWR register, shown in
before transmission of a frame can begin. Setting TFWR to larger values reduces the risk of transmit FIFO
underrun due to system bus latency.
Table 11-18
Freescale Semiconductor
31–2
Bits
1–0
Reset
Reset
Field
Field
Addr
R/W
R/W
describes the TFWR fields.
X_WMRK
31
15
Name
—
MCF5272 ColdFire
Reserved, should be cleared.
Transmit FIFO watermark. Frame transmission begins when the number of bytes selected by this
field are written into the transmit FIFO, if an end of frame has been written to the FIFO, or if the
FIFO is full before the selected number of bytes are written. The options are:
0X 64 bytes written to transmit FIFO
10 128 bytes written to transmit FIFO
11 192 bytes written to transmit FIFO
Figure 11-15. Transmit FIFO Watermark (TFWR)
Figure
Table 11-18. TFWR Field Descriptions
11-15, controls the amount of data required in the transmit FIFO
®
Integrated Microprocessor User’s Manual, Rev. 3
0000_0000_0000_00
0000_0000_0000_0000
—
MBAR + 0x8E4
Read/Write
Read/Write
—
Description
2
X_WMRK
1
Ethernet Module
00
16
0
11-21
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