MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 213

• Manufacturer Part Number: MCF5272VM66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, UART, Ethernet, SPI, USB, QSPI
• Maximum Clock Frequency: 166 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.4 V to 1.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 10
DMA Controller
The MCF5272 has a one-channel DMA controller that supports memory-to-memory DMA transfers that
can be used for block data moves. This chapter describes in detail its signals, registers, and operating
modes.
10.1
A source and destination address must be specified for any dual-address DMA transfer. These addresses
can have different data transfer types, but there is always a read from the source address followed by a
write to the destination address. On the MCF5272, sources and destinations can be SDRAM, external
SRAM, or on-chip peripheral in any combination.
Note that transfers to on-chip peripherals are limited by the transfer type supported by a specific peripheral.
Freescale Semiconductor
DMA Data Transfer Types
Memory-to-memory DMA transfers run to completion if the assume request
bit in the system configuration register, SCR[AR], is set. This generally
prevents the CPU from recognizing interrupts and blocks bus accesses by
other on-chip bus masters. It is best not to enable SCR[AR] when the DMA
controller is in use. When AR = 0, the DMA controller allows the CPU and
Ethernet controller to obtain bus access.
MCF5272 ColdFire
Byte (8 bits)
Word (16 bits)
Longword (32 bits)
Burst (4 x longword)
Transfer Type
Table 10-1. DMA Data Transfer Matrix
®
Integrated Microprocessor User’s Manual, Rev. 3
SDRAM External SRAM On-Chip Peripheral
Yes
Yes
Yes
Yes
Source or Destination Address
NOTE
Yes
Yes
Yes
No
Yes
Yes
Yes
No
10-1