DF2378RVFQ34WV Renesas Electronics America, DF2378RVFQ34WV Datasheet - Page 235

MCU 3V 512K I-TEMP PB-FREE 144-L

DF2378RVFQ34WV

Manufacturer Part Number
DF2378RVFQ34WV
Description
MCU 3V 512K I-TEMP PB-FREE 144-L
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2378RVFQ34WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
6.3.10
REFCR specifies DRAM/synchronous DRAM interface refresh control.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
Bit
15
14
13
12
Note:
Bit Name
CMF
CMIE
RCW1
RCW0
* Only 0 can be written, to clear the flag.
Refresh Control Register (REFCR)
Initial Value
0
0
0
0
R/W
R/(W) *
R/W
R/W
R/W
Description
Compare Match Flag
Status flag that indicates a match between the
values of RTCNT and RTCOR.
[Clearing conditions]
[Setting condition]
When RTCOR = RTCNT
Compare Match Interrupt Enable
Enables or disables interrupt requests (CMI) by the
CMF flag when the CMF flag is set to 1.
This bit is valid when refresh control is not
performed. When the refresh control is performed,
this bit is always cleared to 0 and cannot be
modified.
0: Interrupt request by CMF flag disabled
1: Interrupt request by CMF flag enabled
CAS-RAS Wait Control
These bits select the number of wait cycles to be
inserted between the CAS assert cycle and RAS
assert cycle in a DRAM/synchronous DRAM
refresh cycle.
00: Wait state not inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
When 0 is written to CMF after reading CMF = 1
while the RFSHE bit is cleared to 0
When CBR refreshing is executed while the
RFSHE bit is set to 1
Rev.7.00 Mar. 18, 2009 page 167 of 1136
Section 6 Bus Controller (BSC)
REJ09B0109-0700

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