DF2378RVFQ34WV Renesas Electronics America, DF2378RVFQ34WV Datasheet - Page 740

MCU 3V 512K I-TEMP PB-FREE 144-L

DF2378RVFQ34WV

Manufacturer Part Number
DF2378RVFQ34WV
Description
MCU 3V 512K I-TEMP PB-FREE 144-L
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2378RVFQ34WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 13 8-Bit Timers (TMR)
13.8.3
During the T
signal is inhibited even if a compare match event occurs as shown in figure 13.12.
When using the TMR, ICR input capture is in contention with compare match in the same way as
writes to the TCOR. In such cases input capture has precedence and the compare match signal is
inhibited.
Rev.7.00 Mar. 18, 2009 page 672 of 1136
REJ09B0109-0700
φ
Address
Internal write signal
TCNT
TCOR
Compare match signal
Contention between TCOR Write and Compare Match
Figure 13.12 Contention between TCOR Write and Compare Match
2
state of a TCOR write cycle, the TCOR write has priority and the compare match
TCOR write cycle by CPU
T
1
N
N
TCOR address
T
2
TCOR write data
Inhibited
N + 1
M

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