HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 108

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
Single Data Addressing: DSP instructions include two single data transfer instructions
(MOVS.W, MOVS.L) that load data into, or store data from, a DSP register. With these
instructions, one of registers R2 to R5 is used as the single data transfer address register (As).
The following four kinds of addressing can be used with single data transfer instructions.
1. Non-update address register addressing:
2. Addition index register addressing:
3. Increment address register addressing:
4. Decrement address register addressing:
The R8 register is the index register (Is) for the address pointer (As). Single data transfer
addressing is shown in figure 2.13.
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REJ09B0254-0600
The As register is an address pointer. It is not updated.
The As register is an address pointer. After a data transfer, the value of the Is register is added
to the As register (post-increment).
The As register is an address pointer. After a data transfer, the As register is incremented by 2
or 4 (post-increment).
The As register is an address pointer. Before a data transfer, –2 or –4 is added to the As
register (i.e. 2 or 4 is subtracted) (pre-decrement).
−2/−4 (DEC)
+2/+4 (INC)
+0 (no update)
Note: Four address processing methods:
Figure 2.13 Single Data Transfer Addressing
1. No update
2. Index register addition (Is)
3. Increment
4. Decrement
31
R8[Is]
ALU
0
31
R2[As]
R3[As]
R4[As]
R5[As]
Post-increment
Pre-decrement
0
MAB
31
0
CAB