HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 405
HD6417727BP100BV
Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP100BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 405 of 1098
- Download datasheet (7Mb)
12.3.5
Setting bits A0BST (1, 0), A5BST (1, 0), and A6BST (1, 0) in BCR1 to a non-zero value allows
burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed
access to ROM that has a nibble access function. The timing for nibble access to burst ROM is
shown in figure 12.22. Two wait cycles are set. Basically, access is performed in the same way as
for normal space, but when the first cycle ends the CS0 signal is not negated, and only the address
is changed before the next access is executed. When 8-bit ROM is connected, the number of
consecutive accesses can be set as 4, 8, or 16 by bits A0BST (1, 0), A5BST (1, 0), or A6BST (1,
0). When 16-bit ROM is connected, 4 or 8 can be set in the same way. When 32-bit ROM is
connected, only 4 can be set.
WAIT pin sampling is performed in the first access if one or more wait states are set, and is
always performed in the second and subsequent accesses.
Even if no wait state insertion is specified in burst ROM interface settings, two wait cycles are
automatically inserted in the second and subsequent accesses as shown in figure 12.23.
However, the WAIT signal is ignored in the following three cases:
•
•
•
When writing to an external address area using DMA 16-byte transfer in dual address mode
When transferring data from a DACK-equipped external device to an external address area
using DMA 16-byte transfer in single address mode
During cache write-back access
Burst ROM Interface
Rev.6.00 Mar. 27, 2009 Page 347 of 1036
Section 12 Bus State Controller (BSC)
REJ09B0254-0600
Related parts for HD6417727BP100BV
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT STARTER FOR M16C/29
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C/2D
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
R0K33062P STARTER KIT
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C/23 E8A
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C/25
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER H8S2456 SHARPE DSPLY
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C38C
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C35C
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8CL3AC+LCD APPS
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR RX610
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R32C/118
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT DEV RSK-R8C/26-29
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR SH7124
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR H8SX/1622
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT DEV FOR SH7203
Manufacturer:
Renesas Electronics America
Datasheet: