M30620FCAFP#D3 Renesas Electronics America, M30620FCAFP#D3 Datasheet - Page 140
![IC M16C MCU FLASH 128K 100LQFP](/photos/28/61/286112/100-bqfp__prqp0100jb-a_sml.jpg)
M30620FCAFP#D3
Manufacturer Part Number
M30620FCAFP#D3
Description
IC M16C MCU FLASH 128K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30620FCAFP#D3
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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UART2 Special Mode Register
Figure 1.16.27. Functional block diagram for I
Table 1.16.9. Features in I
10
11
1
2
3
4
5
6
7
8
9
Note 1: Make the settings given below when I
Note 2: Follow the steps given below to switch from a factor to another.
Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.
Factor of interrupt number 10 (Note 2)
Factor of interrupt number 15 (Note 2)
Factor of interrupt number 16 (Note 2)
UART2 transmission output delay
P7
P7
P7
DMA1 factor at the time when 1 1 0 1 is assigned
to the DMA request factor selection bits
Noise filter width
Reading P7
Initial value of UART2 output
0
1
2
P7
P7
P7
at the time when UART2 is in use
at the time when UART2 is in use
at the time when UART2 is in use
P7
0
2
1
/TxD
/CLK
/RxD
1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.
0
2
2
through P7
2
/SDA
/SCL
Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register.
Disable the RTS/CTS function. Choose the MSB First function.
1
Function
Noize
Filter
Noize
Filter
2
Noize
Filter
Selector
conforming to the simplified I C bus
Digital delay
(Divider)
Timer
Selector
Selector
UART2
Falling edge
detection
2
C mode
Timer
I/O
IICM=1
IICM=0
SDDS=1 and
DL 000
SDDS=0
or DL=000
IICM=1
UART2
IICM=0
UART2
D
(Port P7
T
I/O
Q
Start condition
detection
Stop condition
detection
Timer
I/O
Q
IICM=1
IICM=0
1
R
output data latch)
2
C mode is in use.
L-synchronous
output enabling
bit
External clock
Internal clock
Data bus
Port reading
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7
UART2 transmission
TxD
UART2 reception
Bus collision detection
UART2 reception
Not delayed
RxD
CLK
15ns
Reading the terminal when 0 is
assigned to the direction register
H level (when 0 is assigned to
the CLK polarity select bit)
SDHI
SWC2
IICM=1 (SDDS=0) or
DL=000 (SDDS=1)
IICM=0 or
DL 000 (SDDS=1)
2
2
2
2
S
R
(output)
(input)
Analog
Q
delay
Arbitration
Reception register
CLK
control
ALS
2
Bus busy
C mode
Normal mode
UART2
Falling edge of 9 bit
UART2
Bus collision
detection
9th pulse
Transmission
register
SWC
D
D
UART2
T
T
Q
Q
1
of the direction register.
ACK
IICM=1
IICM=0
NACK
IICM=1
and IICM2=0
IICM=0
or IICM2=1
IICM=1
and IICM2=0
IICM=0
or IICM2=1
Bus collision/start, stop condition
detection interrupt request
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Start condition detection or stop
condition detection
SDA (input/output) (Note 3)
Acknowledgment detection (ACK)
50ns
Reading the terminal regardless of the
value of the direction register
The value set in latch P7
selected
No acknowledgment detection (NACK)
Acknowledgment detection (ACK)
Delayed
SCL (input/output)
P7
UART2 reception/ACK interrupt
request, DMA1 request
UART2 transmission/
NACK interrupt request
2
I
2
C mode (Note 1)
M16C / 62A Group
Mitsubishi microcomputers
0
when the port is
To DMA0
To DMA0, DMA1
137
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