M30620FCAFP#D3 Renesas Electronics America, M30620FCAFP#D3 Datasheet - Page 197
![IC M16C MCU FLASH 128K 100LQFP](/photos/28/61/286112/100-bqfp__prqp0100jb-a_sml.jpg)
M30620FCAFP#D3
Manufacturer Part Number
M30620FCAFP#D3
Description
IC M16C MCU FLASH 128K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30620FCAFP#D3
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Timing (Vcc = 3V)
194
Switching characteristics (referenced to V
Table 1.23.39. Memory expansion and microprocessor modes
Note 2: Specify a product of -40°C to 85°C to use it.
Note: Calculated according to the BCLK frequency as follows:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
h(RD-CS)
h(WR-CS)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
d(DB-WR)
h(WR-DB)
d(BCLK-ALE)
h(BCLK-ALE)
d(AD-ALE)
h(ALE-AD)
d(AD-RD)
d(AD-WR)
d(BCLK-RD)
h(BCLK-RD)
dZ(RD-AD)
Symbol
th(RD – AD) =
th(WR – AD) =
th(RD – CS) =
th(WR – CS) =
td(DB – WR) =
th(WR – DB) =
td(AD – ALE) =
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
RD signal output delay time
WR signal output delay time
Data output hold time (BCLK standard)
Data output delay time (WR standard)
ALE signal output hold time(Address standard)
Address output floating start time
Address output hold time (BCLK standard)
Chip select output delay time
Chip select output hold time (WR standard)
RD signal output hold time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (WR standard)
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (Address standard)
Post-address RD signal output delay time
Post-address WR signal output delay time
Address output delay time
Address output hold time (RD standard)
Address output hold time (WR standard)
(when accessing external memory area with wait, and select multiplexed bus)
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
10
Parameter
85
10
10
10
10
10
10
9
o
9
9
9
9
9
9
X 3
C (Note 2), CM15=“1” unless otherwise specified)
– 80
– 45
[ns]
[ns]
[ns]
[ns]
[ns]
[ns]
[ns]
CC
= 3V, V
Measuring condition
Figure 1.23.7
SS
= 0V at Topr = – 20
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
Min.
– 4
50
Standard
4
4
0
0
4
0
0
o
Max.
C to 85
60
60
60
60
80
60
8
Unit
M16C / 62A Group
o
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Mitsubishi microcomputers
C / – 40
V
CC
o
= 3V
C to
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