R8A77850AADBGV Renesas Electronics America, R8A77850AADBGV Datasheet - Page 1048
R8A77850AADBGV
Manufacturer Part Number
R8A77850AADBGV
Description
IC SUPERH MCU 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850AADBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850AADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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20. Graphics Data Translation Accelerator (GDTA)
Table 20.8 shows ARGB8888 conversion sequence shown in figure 20.4.
No. in the table corresponds to the number used in figure 20.4. (1) and (2) correspond to the
numbers in figure 20.3.
Table 20.8 ARGB8888 Conversion Sequence
Rev.1.00 Jan. 10, 2008 Page 1016 of 1658
REJ09B0261-0100
No. Operation
(1) Input data
(2) Rearrangement YUV data is rearranged according to the format indicated in the display
(3) Color
reading
information
reading
Description
YUV-separated input data stored in DDR2-SDRAM is read into the GDTA.
The input data includes padding data with the specified input Y (UV)
padding size, but the GDTA excludes this padding data when reading the
data. However, if the input frame width is not on a 32-byte boundary,
padding data of the amount for 32-byte boundary adjustment is read into the
GDTA. Transfer of data from the DDR2-SDRAM to the GDTA is in 32 byte
units, so that the input data size should be an integral multiple of 32 bytes
for one line (frame width + input padding). If there are deviations in the
specified padding sizes for Y and U/V, operation is not guaranteed.
image of figure 20.3.
(When converting from YUV 4:2:0 to YUV 4:2:2, because the data quantity
for UV is 1/2 that for Y, the UV data in even lines is used for the UV data in
odd lines. For example, the UV data in line 0 is also used in line 1.)
Data converted in (2) is used as the address of the color conversion table
stored in buffer RAM 0 (CLPLPR setting address + converted data), and
color information is read from buffer RAM 0.
(Converted data: Data converted in (2) is shifted two bits to the left and
added to be the RAM 0 address.)
(Color information is read from the buffer RAM 0 address calculated by
adding the Y value read from DDR2-SDRAM to the buffer RAM 0 palette
pointer value (the address set in CLPLPR). (Same for U and V))
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