R8A77850AADBGV Renesas Electronics America, R8A77850AADBGV Datasheet - Page 884
R8A77850AADBGV
Manufacturer Part Number
R8A77850AADBGV
Description
IC SUPERH MCU 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850AADBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850AADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 884 of 1694
- Download datasheet (9Mb)
19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 852 of 1658
REJ09B0261-0100
Bit
13, 12
11
10
9
8
7 to 0
Bit Name
⎯
⎯
RINT
HBK
⎯
VBK
Initial
Value
All 0
0
0
0
0
All 0
R/W
R
R
R
R
R
R
Internal
Update
⎯
None
⎯
None
None
⎯
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Vertical Blanking Flag
0: Indicates the interval to the next display end
1: Indicates the interval, after clearing the VBK
Reserved
This bit is always read as 0. The write value
should always be 0.
Raster Interrupt Flag
0: Indicates the interval from the start of the next
1: After clearing the RINT bit using either the
Horizontal Blanking Flag
0: Indicates the interval, after clearing to 0 the
1: Indicates the interval, after clearing the HBK
Reserved
These bits are always read as 0. The write value
should always be 0.
after clearing to 0 the VBK bit using either the
DRES bit in DSYSR or the VBCL bit in
DSRCR.
bit using either the DRES bit in DSYSR or the
VBCL bit in DSRCR, from the first vertical
blanking interval until the VBK bit is again
cleared to 0. (field units)
display until raster scans set in the raster
interrupt offset register have elapsed, after
clearing to 0 the RINT bit using either the
DRES bit in DSYSR or the RICL bit in
DSRCR.
DRES bit in DSYSR or the RICL bit in
DSRCR, indicates the interval from the start
of the next display after raster scans set in the
raster interrupt offset register have elapsed
until the bit is again cleared to 0.
HBK bit using the DRES bit in DSYSR or the
HBCL bit in DSRCR, to the next horizontal
blanking.
bit using either the DRES bit in DSYSR or the
HBCL bit in DSRCR, from the first horizontal
blanking interval until the HBK bit is again
cleared to 0.
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