R8A77850AADBGV Renesas Electronics America, R8A77850AADBGV Datasheet - Page 255
R8A77850AADBGV
Manufacturer Part Number
R8A77850AADBGV
Description
IC SUPERH MCU 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850AADBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850AADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.3.2
When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is prefetched from a
cacheable area, the cache operates as follows:
1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual
2. The tag, read from each way, is compared with bits [28:10] of the physical address resulting
3. Cache hit
4. Cache miss (no write-back)
5. Cache miss (with write-back)
write-back buffer is then written back to external memory.
address bits [12:5].
from virtual address translation by the MMU:
⎯ If there is a way whose tag matches and its V bit is 1, see No. 3.
⎯ If there is no way whose tag matches and the V bit is 1, and the U bit of the way which is
⎯ If there is no way whose tag matches and the V bit is 1, and the U bit of the way which is
Then the LRU bits are updated to indicate the hitted way is the latest one.
Data is read into the cache line on the way, which is selected to replace, from the physical
address space corresponding to the virtual address. Data reading is performed, using the
wraparound method, in order from the quad-word data (8 bytes) including the cache-missed
data. In the prefetch operation the CPU doesn't wait the data arrives. While the one cache line
of data is being read, the CPU can execute the next processing. When reading of one line of
data is completed, the tag corresponding to the physical address is recorded in the cache, 1 is
written to the V bit and 0 is written to the U bit on the way. And the LRU bit is updated to
indicate the way is latest one.
The tag and data field of the cache line on the way which is selected to replace are saved in the
write-back buffer. Then data is read into the cache line on the way which is selected to replace
from the physical address space corresponding to the virtual address. Data reading is
performed, using the wraparound method, in order from the quad-word data (8 bytes)
including the cache-missed data. In the prefetch operation the CPU doesn't wait the data
arrives. While the one cache line of data is being read, the CPU can execute the next
processing. And the LRU bits are updated to indicate the way is latest one. The data in the
write-back buffer is then written back to external memory.
selected to replace using the LRU bits is 0, see No. 4.
selected to replace using the LRU bits is 1, see No. 5.
Prefetch Operation
Rev.1.00 Jan. 10, 2008 Page 223 of 1658
REJ09B0261-0100
8. Caches
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