R8A77850AADBGV Renesas Electronics America, R8A77850AADBGV Datasheet - Page 125
R8A77850AADBGV
Manufacturer Part Number
R8A77850AADBGV
Description
IC SUPERH MCU 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850AADBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850AADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 125 of 1694
- Download datasheet (9Mb)
5.2.4
The non-support detection exception register (EXPMASK) is used to enable or disable the
generation of exceptions in response to the use of any of functions 1 to 3 listed below. The
functions of 1 to 3 are planned not to be supported in the future SuperH-family products. The
exception generation functions of EXPMASK can be used in advance of execution; the detection
function then checks for the use of these functions in the software. This will ease the transfer of
software to the future SuperH-family products that do not support the respective functions.
1. Handling of an instruction other than the NOP instruction in the delay slot of the RTE
2. Handling of the SLEEP instruction in the delay slot of the branch instruction.
3. Performance of IC/OC memory-mapped associative write operations.
According to the value of EXPMASK, functions 1 and 2 can generate a slot illegal instruction
exception, and 3 can generate a data address error exception.
Generation of each exception can be disabled by writing 1 to the corresponding bit in EXPMASK.
However, it is recommended that the above functions should not be used when making a program
to maintain the compatibility with the future products.
Use the store instruction of the CPU to update EXPMASK. After updating the register and then
reading the register once, execute either of the following instructions. Executing either instruction
guarantees the operation with the updated register value.
• Execute the RTE instruction.
• Execute the ICBI instruction for any address (including non-cacheable area).
Initial value:
Initial value:
instruction.
R/W:
R/W:
Bit:
Bit:
Non-Support Detection Exception Register (EXPMASK)
31
15
R
R
−
−
0
0
30
14
R
R
−
0
−
0
29
13
R
R
−
0
−
0
28
12
R
R
−
0
−
0
27
11
R
R
−
0
−
0
26
10
R
R
−
−
0
0
25
R
R
−
0
9
−
0
24
R
R
−
0
8
−
0
23
R
R
−
0
7
−
0
22
R
R
−
0
6
−
0
Rev.1.00 Jan. 10, 2008 Page 93 of 1658
21
R
R
−
0
5
−
0
CAW
R/W
MM
20
R
0
4
1
−
19
5. Exception Handling
R
R
0
3
0
−
−
REJ09B0261-0100
18
R
R
−
0
2
0
−
BRDS
R/W
SLP
17
R
−
0
1
1
R/W
RTE
DS
16
R
1
−
0
0
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