R8A77850AADBGV Renesas Electronics America, R8A77850AADBGV Datasheet - Page 768
R8A77850AADBGV
Manufacturer Part Number
R8A77850AADBGV
Description
IC SUPERH MCU 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850AADBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850AADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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15. Clock Pulse Generator (CPG)
15.2
Table 15.1 shows the CPG pin configuration.
Table 15.1 CPG Pin Configuration
Notes: 1. The clock operating mode and the clock input mode depend on the states of the mode
Rev.1.00 Jan. 10, 2008 Page 736 of 1658
REJ09B0261-0100
Pin Name
MODE0,
MODE1,
MODE2,
MODE3,
and MODE4*
MODE10
XTAL
EXTAL
CLKOUT*
CLKOUTENB
2. For details on ensuring the AC timing of the CLKOUT pin, see the section about
2
Input/Output Pins
pins on a power-on reset via the PRESET pin.
electrical characteristics. Note the relationship between the input frequency and
multiplication rate of a crystal oscillator circuit.
1
Function
Mode Pins
0,1,2,3,4
Clock
operating
mode*
Mode Pin 10
Clock input
mode*
Clock Pins
Clock Output
Enabled
1
1
I/O
Input
Input
Output
Input
Output
Output
Description
Select the clock operating mode
These pins are multiplexed with the following pins.
MODE0: the IRL4 (INTC), FD4 (FLCTL), and PL4 (GPIO) pins
MODE1: the IRL5 (INTC), FD5 (FLCTL), and PL3 (GPIO) pins
MODE2: the IRL6 (INTC), FD6 (FLCTL), and PL2 (GPIO) pins
MODE3: the IRL7 (INTC), FD7 (FLCTL), and PL1 (GPIO) pins
MODE4: the SCIF3_TXD (SCIF channel 3), FCLE (FLCTL), and PN5
(GPIO) pins
Selects whether the crystal resonator is used
When MODE10 is set to the low level, the external clock is input from
the EXTAL pin.
When MODE10 is set to the high level, the crystal resonator is
connected directly to the EXTAL and XTAL pins.
MODE10 is multiplexed with the SCIF4_RXD (SCIF channel 4), FD2
(FLCTL), and PN1 (GPIO) pins.
Connected to a crystal resonator
Used to input an external clock or connected to a crystal resonator.
Used to output a local bus clock
The low level is output when the output clock of the CLKOUT is
unstable.
When the input to the PRESET pin is the low level, the high level is
output regardless of the status of the output clock on the CLKOUT
pin.
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