UPD78F0500MC-5A4-A Renesas Electronics America, UPD78F0500MC-5A4-A Datasheet - Page 559

• Manufacturer Part Number: UPD78F0500MC-5A4-A
• Description: MCU 8BIT FLASH SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500MC-5A4-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Note The signal of this bit is invalid while IICE0 is 0.
Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting.
Cautions concerning set timing
• For master reception:
• For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1 during
• Cannot be set to 1 at the same time as stop condition trigger (SPT0).
• Setting the STT0 bit to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (STT0 = 0)
• Cleared by setting SST0 bit to 1 while communication
• Cleared by loss in arbitration
• Cleared after start condition is generated by master device
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
STT0
reservation is prohibited.
0
1
Note
2. IICRSV: Bit 0 of IIC flag register (IICF0)
Do not generate a start condition.
When bus is released (in standby state, when IICBSY = 0):
When a third party is communicating:
In the wait state (when master device):
STCF:
Generates a restart condition after releasing the wait.
If this bit is set (1), a start condition is generated (startup as the master).
• When communication reservation function is enabled (IICRSV = 0)
• When communication reservation function is disabled (IICRSV = 1)
Functions as the start condition reservation flag. When set to 1, automatically generates a start condition
after the bus is released.
Even if this bit is set (1), the STT0 is cleared and the STT0 clear flag (STCF) is set (1). No start condition is
generated.
Bit 7 of IIC flag register (IICF0)
Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has
been cleared to 0 and slave has been notified of final reception.
the wait period that follows output of the ninth clock.
Figure 18-5. Format of IIC Control Register 0 (IICC0) (3/4)
Start condition trigger
Condition for setting (STT0 = 1)
• Set by instruction
CHAPTER 18 SERIAL INTERFACE IIC0
559