UPD78F0500MC-5A4-A Renesas Electronics America, UPD78F0500MC-5A4-A Datasheet - Page 581

• Manufacturer Part Number: UPD78F0500MC-5A4-A
• Description: MCU 8BIT FLASH SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500MC-5A4-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
18.5.14 Communication reservation
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(1) When communication reservation function is enabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 0)
To start master device communications when not currently using a bus, a communication reservation can be made
to enable transmission of a start condition when the bus is released. There are two modes under which the bus is
not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
If bit 1 (STT0) of IICC0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition is
automatically generated and wait state is set.
If an address is written to IIC shift register 0 (IIC0) after bit 4 (SPIE0) of IICC0 was set to 1, and it was detected by
generation of an interrupt request signal (INTIIC0) that the bus was released (detection of the stop condition), then
the device automatically starts communication as the master. Data written to IIC0 before the stop condition is
detected is invalid.
When STT0 has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
• If the bus has been released ........................................ a start condition is generated
• If the bus has not been released (standby mode)......... communication reservation
Check whether the communication reservation operates or not by using MSTS0 bit (bit 7 of IIC status register 0
(IICS0)) after STT0 bit is set to 1 and the wait time elapses.
The wait periods, which should be set via software, are listed in Table 18-6.
Figure 18-20 shows the communication reservation timing.
released when bit 6 (LREL0) of IIC control register 0 (IICC0) was set to 1).
CLX0
0
0
0
0
0
0
0
0
1
1
1
SMC0
0
0
0
0
1
1
1
1
1
1
1
CL01
0
0
1
1
0
0
1
1
0
0
1
Table 18-6. Wait Periods
CL00
0
1
0
1
0
1
0
1
0
1
0
46 clocks
86 clocks
172 clocks
34 clocks
30 clocks
60 clocks
12 clocks
18 clocks
36 clocks
CHAPTER 18 SERIAL INTERFACE IIC0
Wait Period
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