UPD78F1143AGA-HAB-AX Renesas Electronics America, UPD78F1143AGA-HAB-AX Datasheet - Page 207
UPD78F1143AGA-HAB-AX
Manufacturer Part Number
UPD78F1143AGA-HAB-AX
Description
MCU 16BIT 78K0R/KX3 64-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGA-HAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGA-HAB-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 207 of 880
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Address: F01BEH, F01BFH
Symbol
(12) Timer output mode register 0 (TOM0)
TOM0
Caution Be sure to clear bits 15 to 7 to “0”.
Remark
TOM0 is used to control the timer output mode of each channel.
When a channel is used for the single-operation function, set the corresponding bit of the channel to be used
to 0.
When a channel is used for the combination-operation function (PWM output, one-shot pulse output, or
multiple PWM output), set the corresponding bit of the master channel to 0 and the corresponding bit of the
slave channel to 1.
The setting of each channel n by this register is reflected at the timing when the timer output signal is set or
reset while the timer output is enabled (TOE0n = 1).
TOM0 can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TOM0 can be set with an 8-bit memory manipulation instruction with TOM0L.
Reset signal generation clears this register to 0000H.
TOM
0n
15
0
1
0
n: Channel number, m: Slave channel number
n = 0 to 6 (n = 0, 2, 4 for master channel)
n < m ≤ 6 (where m is a consecutive integer greater than n)
Toggle mode (to produce toggle output by timer interrupt request signal (INTTM0n))
Combination-operation mode (output is set by the timer interrupt request signal (INTTM0n) of the master
channel, and reset by the timer interrupt request signal (INTTM0m) of the slave channel)
14
0
Figure 6-20. Format of Timer Output Mode Register 0 (TOM0)
After reset: 0000H
13
0
12
0
11
0
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
R/W
10
0
Control of timer output mode of channel n
9
0
8
0
7
0
TOM
06
6
TOM
05
5
TOM
04
4
TOM
03
3
TOM
02
2
TOM
01
1
TOM
00
205
0
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