UPD78F1143AGA-HAB-AX Renesas Electronics America, UPD78F1143AGA-HAB-AX Datasheet - Page 67
UPD78F1143AGA-HAB-AX
Manufacturer Part Number
UPD78F1143AGA-HAB-AX
Description
MCU 16BIT 78K0R/KX3 64-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGA-HAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGA-HAB-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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3.2.2 General-purpose registers
general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
(AX, BC, DE, and HL).
absolute names (R0 to R7 and RP0 to RP3).
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of
Caution It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
SP←SP−2
SP←SP−4
SP
SP−2
SP−1
SP
SP−4
SP−3
SP−2
SP−1
→
→
↑
↑
↑
↑
↑
↑
↑
↑
CALL, CALLT instructions
PUSH rp instruction
Register pair higher
Figure 3-15. Data to Be Saved to Stack Memory
Register pair lower
PC19 to PC16
(4-byte stack)
PC15 to PC8
PC7 to PC0
00H
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17854EJ9V0UD
SP←SP−2
SP←SP−4
SP
SP−2
SP−1
SP
SP−4
SP−3
SP−2
SP−1
→
↑
↑
↑
→
↑
↑
↑
↑
↑
Interrupt, BRK instruction
PUSH PSW instruction
PC19 to PC16
(4-byte stack)
PC15 to PC8
PC7 to PC0
PSW
PSW
00H
65
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