UPD78F1144AGK-GAJ-AX Renesas Electronics America, UPD78F1144AGK-GAJ-AX Datasheet - Page 434
UPD78F1144AGK-GAJ-AX
Manufacturer Part Number
UPD78F1144AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1144AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1144AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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SCRmn
SDRmn
SMRmr
(e) Serial mode register mr (SMRmr)
(f) Serial communication operation setting register mn (SCRmn)
(g) Serial data register mn (SDRmn) (lower 8 bits: RXDq)
Caution For the UART reception, be sure to set SMRmr of channel r that is to be paired with channel n.
Remark
TXEmn
CKSmr
0/1
Same setting value as CKSmn
15
15
15
0
Figure 11-79. Example of Contents of Registers for UART Reception of UART
m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 13,
r: Channel number (r = n − 1), q: UART number (q = 0, 1, 3)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
CCSmr
RXEmn
14
14
14
0
1
: Setting is fixed in the UART reception mode,
DAPmn
13
13
13
0
0
Baud rate setting
CKPmn
12
12
12
0
0
11
11
11
0
0
CHAPTER 11 SERIAL ARRAY UNIT
EOCmn
(UART0, UART1, UART3) (2/2)
10
10
10
0
1
User’s Manual U17854EJ9V0UD
PTCmn1
0/1
9
0
9
9
PTCmn0
STSmr
0/1
8
0
8
8
0
DIRmn
0/1
0
7
7
7
SISmr0
0
6
0
6
6
: Setting disabled (set to the initial value)
SLCmn1
5
1
0
5
5
Receive data register
SLCmn0
4
0
4
1
4
Interrupt sources of channel r
0: Transfer end interrupt
1: Buffer empty interrupt
RXDq
3
0
3
0
3
DLSmn2
MDmr2
0
2
2
1
2
MDmr1
DLSmn1
0/1
1
1
1
1
MDmr0
DLSmn0
0/1
0/1
0
0
0
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