UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 318
UPD70F3737GF-GAS-AX
Manufacturer Part Number
UPD70F3737GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3737GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3737GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 7-61. Example of Resolving Problem When Two Capture Registers Are Used By Using Overflow
Note The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software.
<1> The TPnCCR0 register is read (the default value of the TIPn0 pin input is set).
<2> The TPnCCR1 register is read (the default value of the TIPn1 pin input is set).
<3> An overflow occurs. The TPnOVF0 and TPnOVF1 flags are set to 1 in the overflow interrupt
<4> The TPnCCR0 register is read.
<5> The TPnCCR1 register is read.
<6> Same as <3>.
Remark
TPnCCR0 register
TPnCCR1 register
INTTPnOV signal
TPnOVF0 flag
TPnOVF1 flag
servicing, and the TPnOVF bit is cleared to 0.
The TPnOVF0 flag is read. The TPnOVF0 flag is 1, so it is cleared to 0.
Because the TPnOVF0 flag was 1, the pulse width can be calculated by (10000H + D
The TPnOVF1 flag is read. The TPnOVF1 flag is 1, so it is cleared to 0 (the TPnOVF0 flag was
cleared in <4>; the TPnOVF1 flag remained 1).
Because the TPnOVF1 flag is 1, the pulse width can be calculated by (10000H + D
(correct).
TIPn0 pin input
TIPn1 pin input
16-bit counter
TPnOVF bit
n = 0 to 5
TPnCE bit
FFFFH
0000H
Note
Note
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
D
00
User’s Manual U18953EJ5V0UD
<1>
D
10
<2>
Interrupt
D
00
<3>
D
D
01
10
<4>
D
11
<5> <6>
D
01
D
11
01
− D
11
00
− D
).
10
)
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