UPD70F3743GJ-GAE-AX Renesas Electronics America, UPD70F3743GJ-GAE-AX Datasheet - Page 513
UPD70F3743GJ-GAE-AX
Manufacturer Part Number
UPD70F3743GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3743GJ-GAE-AX.pdf
(911 pages)
Specifications of UPD70F3743GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
128
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3743GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3743GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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- Download datasheet (6Mb)
V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
(5) Allowable baud rate range during reception
The baud rate error range at the destination that is allowable during reception is shown below.
Caution The baud rate error during reception must be set within the allowable error range using the
As shown in Figure 15-17, the receive data latch timing is determined by the counter set using the UAnCTL2
register following start bit detection. The transmit data can be normally received if up to the last data (stop bit) can
be received in time for this latch timing.
When this is applied to 11-bit reception, the following is the theoretical result.
Remark
FL = (Brate)
Minimum allowable transfer rate: FLmin = 11 × FL −
transfer rate
transfer rate
transfer rate
Maximum
Brate: UARTAn baud rate (n = 0 to 3)
k:
FL:
Latch timing margin: 2 clocks
allowable
allowable
Minimum
UARTAn
following equation.
n = 0 to 3
Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0 to 3)
1-bit data length
−
1
Figure 15-17. Allowable Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
Bit 0
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Bit 0
FL
Bit 0
Bit 1
Bit 1
Bit 1
1 data frame (11 × FL)
FLmin
k − 2
2k
FLmax
× FL =
Bit 7
Bit 7
Bit 7
21k + 2
Parity bit
2k
Parity bit
Parity bit
FL
Stop bit
Stop bit
Stop bit
Page 497 of 892
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