UPD70F3743GJ-GAE-AX Renesas Electronics America, UPD70F3743GJ-GAE-AX Datasheet - Page 899

• Manufacturer Part Number: UPD70F3743GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3743GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
Interrupt/
exception
processing
function
Function
ISPR register
Restoration
from software
exception
processing
Illegal opcode
definition
Restoration
from exception
trap
Restoration from
debug trap
INTF0, INTR0
registers
INTF3, INTR3
registers
INTF8, INTR8
registers
INTF9H,
INTR9H
registers
Details of
Function
If an interrupt is acknowledged while the ISPR register is being read in the
interrupt enabled (EI) status, the value of the ISPR register after the bits of the
register have been set by acknowledging the interrupt may be read. To accurately
read the value of the ISPR register before an interrupt is acknowledged, read the
register while interrupts are disabled (DI).
When the EP and NP bits are changed by the LDSR instruction during the
software exception processing, in order to restore the PC and PSW correctly
during recovery by the RETI instruction, it is necessary to set the EP bit back to 1
and the NP bit back to 0 using the LDSR instruction immediately before the RETI
instruction.
Since it is possible to assign this instruction to an illegal opcode in the future, it is
recommended that it not be used.
DBPC and DBPSW can be accessed only during the interval between the
execution of an illegal opcode and the DBRET instruction.
DBPC and DBPSW can be accessed only during the interval between the
execution of the DBTRAP instruction and the DBRET instruction.
When the function is changed from the external interrupt function (alternate
function) to the port function, an edge may be detected. Therefore, clear the
INTF0n and INTR0n bits to 00, and then set the port mode.
Be sure to clear the INTF0n and INTR0n bits to 00 when these registers are not
used as the NMI or INTP0 to INTP3 pins.
When the function is changed from the external interrupt function (alternate
function) to the port function, an edge may be detected. Therefore, clear the
INTF31 and INTR31 bits to 00, and then set the port mode.
The INTP7 pin and RXDA0 pin are alternate-function pins. When using the pin as
the RXDA0 pin, disable edge detection for the INTP7 alternate-function pin (clear
the INTF3.INTF31 bit and the INRT3.INTR31 bit to 0). When using the pin as the
INTP7 pin, stop UARTA0 reception (clear the UA0CTL0.UA0RXE bit to 0).
Be sure to clear the INTF31 and INTR31 bits to 00 when these registers are not
used as INTP7 pin.
When the function is changed from the external interrupt function (alternate
function) to the port function, an edge may be detected. Therefore, clear the
INTF80 and INTR80 bits to 00, and then set the port mode.
The INTP8 pin and RXDA3 pin are alternate-function pins. When using the pin as
the RXDA3 pin, disable edge detection for the INTP8 alternate-function pin (clear
the INTF8.INTF80 bit and the INTR8.INTR80 bit to 0). When using the pin as the
INTP8 pin, stop UARTA3 reception (clear the UA3CTL0.UA3RXE bit to 0).
Be sure to clear the INTF80 and INTR80 bits to 00 when these registers are not
used as INTP8 pin.
When the function is changed from the external interrupt function (alternate
function) to the port function, an edge may be detected. Therefore, clear the
INTF9n and INTR9n bits to 0, and then set the port mode.
Be sure to clear the INTF9n and INTR9n bits to 00 when these registers are not
used as INTP4 to INTP6 pins.
Cautions
APPENDIX E LIST OF CAUTIONS
Page 883 of 892
p. 672
p. 675
p. 677
p. 678
p. 680
p. 682
p. 682
p. 683
p. 683
p. 683
p. 684
p. 684
p. 684
p. 685
p. 685
Page
(30/37)