SAF-XC161CJ-16F40F BB Infineon Technologies, SAF-XC161CJ-16F40F BB Datasheet - Page 23

• Manufacturer Part Number: SAF-XC161CJ-16F40F BB
• Description: IC MCU 16BIT 128KB FLSH 144TQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC161CJ-16F40F BB

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, I²C, SLDM, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 99
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 12x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: 2xASC, 2xSSC, 1xSDLM, 1xI2C, J1850
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 99
• Number Of Timers: 9
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Packages: PG-TQFP-144
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 8.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 12
• Program Memory: 128.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.
Table 3
Address Area
Flash register space
Reserved (Access trap) F8’0000
Reserved for PSRAM
Program SRAM
Reserved for program
memory
Program Flash
Reserved
External memory area
External IO area
TwinCAN registers
External memory area
Data RAMs and SFRs
External memory area
1) Accesses to the shaded areas generate external bus accesses.
2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
3) Not defined register locations return a trap code.
4) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
Data Sheet
peripherals properly.
XC161 Memory Map
4)
Start Loc.
FF’F000
E0’0800
E0’0000
C2’0000
C0’0000
BF’0000
40’0000
20’0800
20’0000
01’0000
00’8000
00’0000
H
H
H
H
H
H
H
H
H
H
H
H
H
1)
End Loc.
FF’FFFF
FF’EFFF
F7’FFFF
E0’07FF
DF’FFFF
C1’FFFF
BF’FFFF
BE’FFFF
3F’FFFF
20’07FF
1F’FFFF
00’FFFF
00’7FFF
21
Table
H
H
H
H
H
H
H
H
H
H
H
H
H
Area Size
4 Kbytes
< 0.5 Mbytes Minus Flash
< 1.5 Mbytes Minus PSRAM
2 Kbytes
< 2 Mbytes
128 Kbytes
64 Kbytes
< 8 Mbytes
< 2 Mbytes
2 Kbytes
< 2 Mbytes
32 Kbytes
32 Kbytes
3) of external RAM and/or ROM can
2)
Functional Description
Notes
3)
registers
Maximum
Minus Flash
–
–
Minus reserved
segment
Minus TwinCAN
–
Minus segment 0
Partly used
–
XC161CJ-16F
Derivatives
V2.4, 2006-08