SAF-XC161CJ-16F40F BB Infineon Technologies, SAF-XC161CJ-16F40F BB Datasheet - Page 45
![IC MCU 16BIT 128KB FLSH 144TQFP](/photos/39/69/396957/qfp144_sml.jpg)
SAF-XC161CJ-16F40F BB
Manufacturer Part Number
SAF-XC161CJ-16F40F BB
Description
IC MCU 16BIT 128KB FLSH 144TQFP
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC161CJ-16F40F_BB.pdf
(88 pages)
Specifications of SAF-XC161CJ-16F40F BB
Core Processor
C166SV2
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, I²C, SLDM, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
99
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 12x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
2xASC, 2xSSC, 1xSDLM, 1xI2C, J1850
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
99
Number Of Timers
9
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Packages
PG-TQFP-144
Max Clock Frequency
40.0 MHz
Sram (incl. Cache)
8.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
12
Program Memory
128.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
3.11
The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and half-
duplex synchronous communication. It may be configured so it interfaces with serially
linked peripheral components, full SPI functionality is supported.
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling three separate interrupt
vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit error and receive error supervise the correct
handling of the data buffer. Phase error and baudrate error detect incorrect serial data.
Summary of Features
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Data Sheet
Master or Slave mode operation
Full-duplex or Half-duplex transfers
Baudrate generation from 20 Mbit/s to 305.18 bit/s (@ 40 MHz)
Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB-first or MSB-first
– Programmable clock polarity: idle low or idle high
– Programmable clock/data phase: data shift with leading or trailing clock edge
Loop back option available for testing purposes
Interrupt generation on transmitter buffer empty condition, receive buffer full
condition, error condition (receive, phase, baudrate, transmit error)
Three pin interface with flexible SSC pin configuration
High Speed Synchronous Serial Channels (SSC0/SSC1)
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Functional Description
XC161CJ-16F
Derivatives
V2.4, 2006-08