SAF-XC161CJ-16F40F BB Infineon Technologies, SAF-XC161CJ-16F40F BB Datasheet - Page 32

• Manufacturer Part Number: SAF-XC161CJ-16F40F BB
• Description: IC MCU 16BIT 128KB FLSH 144TQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC161CJ-16F40F BB

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, I²C, SLDM, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 99
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 12x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: 2xASC, 2xSSC, 1xSDLM, 1xI2C, J1850
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 99
• Number Of Timers: 9
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Packages: PG-TQFP-144
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 8.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 12
• Program Memory: 128.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

The XC161 also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurence
occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 5
time:
Table 5
Exception Condition
Reset Functions:
•
•
•
Class A Hardware Traps:
•
•
•
•
Class B Hardware Traps:
•
•
•
•
Reserved
Software Traps
•
1) Register VECSEG defines the segment where the vector table is located to.
Data Sheet
Hardware Reset
Software Reset
Watchdog Timer
Overflow
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Software Break
Undefined Opcode
PMI Access Error
Protected Instruction
Fault
Illegal Word Operand
Access
TRAP Instruction
shows all of the possible exceptions or error conditions that can arise during run-
Hardware Trap Summary
Trap
Flag
–
NMI
STKOF
STKUF
SOFTBRK
UNDOPC
PACER
PRTFLT
ILLOPA
–
–
Trap
Vector
RESET
RESET
RESET
NMITRAP
STOTRAP
STUTRAP
SBRKTRAP
BTRAP
BTRAP
BTRAP
BTRAP
–
–
30
Vector
Location
xx’0000
xx’0000
xx’0000
xx’0008
xx’0010
xx’0018
xx’0020
xx’0028
xx’0028
xx’0028
xx’0028
[2C
Any
[xx’0000
xx’01FC
in steps of
4
H
H
- 3C
Functional Description
H
H
H
H
H
H
H
H
H
H
H
H
H
1)
]
H
-
] [0B
Trap
Number
00
00
00
02
04
06
08
0A
0A
0A
0A
0F
Any
[00
7F
H
H
H
H
H
H
H
H
H
XC161CJ-16F
H
H
H
H
H
H
]
]
-
-
Derivatives
V2.4, 2006-08
Trap
Priority
III
III
III
II
II
II
II
I
I
I
I
–
Current
CPU
Priority