SAF-XC161CJ-16F40F BB Infineon Technologies, SAF-XC161CJ-16F40F BB Datasheet - Page 46

• Manufacturer Part Number: SAF-XC161CJ-16F40F BB
• Description: IC MCU 16BIT 128KB FLSH 144TQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC161CJ-16F40F BB

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, I²C, SLDM, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 99
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 12x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: 2xASC, 2xSSC, 1xSDLM, 1xI2C, J1850
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 99
• Number Of Timers: 9
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Packages: PG-TQFP-144
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 8.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 12
• Program Memory: 128.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.12
The Serial Data Link Module (SDLM) provides serial communication on a J1850 type
multiplexed serial bus via an external J1850 bus transceiver. The module conforms to
the SAE Class B J1850 specification for variable pulse width modulation (VPW).
General SDLM Features:
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Data Link Operation Features:
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Note: When the SDLM is used with the interface lines assigned to Port 4, the segment
Data Sheet
Compliant to the SAE Class B J1850 specification (VPW)
Class 2 protocol fully supported
Variable Pulse Width (VPW) operation at 10.4 kbit/s
High Speed 4X operation at 41.6 kbit/s
Programmable Normalization Bit
Programmable Delay for transceiver interface
Digital Noise Filter
Power Down mode with automatic wake-up support upon bus activity
Single Byte Header and Consolidated Header supported
CRC generation and checking
Receive and transmit Block Mode
11-Byte Transmit Buffer
Double buffered 11-Byte receive buffer (optional overwrite enable)
Support for In Frame Response (IFR) types 1, 2 and 3
Transmit and Receiver Message Buffers configurable for either FIFO or Byte mode
Advanced Interrupt Handling with 8 separately enabled sources:
– Error, format or bus shorted
– CRC error
– Lost Arbitration
– Break received
– In-Frame-Response request
– Header received
– Complete message received
– Transmit successful
Automatic IFR transmission (Types 1 and 2) for 3-Byte consolidated headers
User configurable clock divider
Bus status flags (IDLE, EOF, EOD, SOF, Tx and Rx in progress)
address output on Port 4 must be limited. CS lines can be used to increase the
total amount of addressable external memory.
Serial Data Link Module (SDLM)
44
Functional Description
XC161CJ-16F
Derivatives
V2.4, 2006-08