SAF-TC1167-128F133HL AD Infineon Technologies, SAF-TC1167-128F133HL AD Datasheet - Page 43

• Manufacturer Part Number: SAF-TC1167-128F133HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC116xr

Specifications of SAF-TC1167-128F133HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 104 KB
• Interface Type: ASC, MLI, MSC, SSC
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel) / 10 bit, 4 Channel
• Packages: PG-LQFP-176
• Max Clock Frequency: 133.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• For Use With: B158-H8690-X-0-7600IN - KIT STARTER TC116X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000602800

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2.4.5
This TC1167 contains one Micro Link Interface, MLI0.
The Micro Link Interface (MLI) is a fast synchronous serial interface to exchange data
between microcontrollers or other devices, such as stand-alone peripheral components.
Figure 9
interfaces.
Figure 9
Features
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Data Sheet
– Static allocation commands offer compatibility with MultiCAN applications that are
Advanced interrupt handling
– Up to 16 interrupt output lines are available. Interrupt requests can be routed
– Message post-processing notifications can be combined flexibly into a dedicated
Synchronous serial communication between an MLI transmitter and an MLI receiver
Different system clock speeds supported in MLI transmitter and MLI receiver due to
full handshake protocol (4 lines between a transmitter and a receiver)
Fully transparent read/write access supported (= remote programming)
Complete address range of target device available
Specific frame protocol to transfer commands, addresses and data
Error detection by parity bit
not list-based.
individually to one of the 16 interrupt output lines.
register field of 256 notification bits.
shows how two microcontrollers are typically connected together via their MLI
Peripheral
Memory
Micro Link Interface
A
Typical Micro Link Interface Connection
System Bus
Controller 1
CPU
Peripheral
MLI
B
39
Peripheral
MLI
C
System Bus
Controller 2
CPU
Peripheral
Memory
D
MCA06061
Introduction
V1.3, 2009-10
TC1167