PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 117
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PIC17C756-16/L
Manufacturer Part Number
PIC17C756-16/L
Description
MICRO CTRL 16K MEMORY OTP 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756-16/L
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- PIC17C756CL PDF datasheet #5
- Current page: 117 of 321
- Download datasheet (3Mb)
14.3
In Master Synchronous mode, the data is transmitted in
a half-duplex manner; i.e. transmission and reception
do not occur at the same time: when transmitting data,
the reception is inhibited and vice versa. The synchro-
nous mode is entered by setting the SYNC
(TXSTA<4>) bit. In addition, the SPEN (RCSTA<7>)
bit is set in order to configure the I/O pins to CK (clock)
and DT (data) lines respectively. The Master mode
indicates that the processor transmits the master clock
on the CK line. The Master mode is entered by setting
the CSRC (TXSTA<7>) bit.
14.3.1
The USART transmitter block diagram is shown in
Figure 14-3. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer TXREG.
TXREG is loaded with data in software. The TSR is not
loaded until the last bit has been transmitted from the
previous load. As soon as the last bit is transmitted, the
TSR is loaded with new data from TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one T
is empty and the TXIF bit is set. This interrupt can be
enabled/disabled by setting/clearing the TXIE bit. TXIF
will be set regardless of the state of bit TXIE and cannot
be cleared in software. It will reset only when new data
is loaded into TXREG. While TXIF indicates the status
of TXREG, TRMT (TXSTA<1>) shows the status of the
TSR. TRMT is a read only bit which is set when the
TSR is empty. No interrupt logic is tied to this bit, so the
user has to poll this bit in order to determine if the TSR
is empty. The TSR is not mapped in data memory, so it
is not available to the user.
Transmission is enabled by setting the TXEN
(TXSTA<5>) bit. The actual transmission will not occur
until TXREG has been loaded with data. The first data
bit will be shifted out on the next available rising edge
of the clock on the TX/CK pin. Data out is stable around
the
(Figure 14-10). The transmission can also be started
by first loading TXREG and then setting TXEN. This is
advantageous when slow baud rates are selected,
since BRG is kept in RESET when the TXEN, CREN,
and SREN bits are clear. Setting the TXEN bit will start
the BRG, creating a shift clock immediately. Normally
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to
Back-to-back transfers are possible.
Clearing TXEN during a transmission will cause the
transmission to be aborted and will reset the transmit-
ter. The RX/DT and TX/CK pins will revert to hi-imped-
ance. If either CREN or SREN are set during a
transmission, the transmission is aborted and the
RX/DT pin reverts to a hi-impedance state (for a recep-
1997 Microchip Technology Inc.
the TSR,
CY
falling
at the end of the current BRG cycle), TXREG
USART Synchronous Master Mode
USART SYNCHRONOUS MASTER
TRANSMISSION
edge
resulting
of
the
in
an
synchronous
empty TXREG.
clock
Preliminary
tion). The TX/CK pin will remain an output if the CSRC
bit is set (internal clock). The transmitter logic is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear the TXEN
bit. If the SREN bit is set (to interrupt an ongoing trans-
mission and receive a single word), then after the sin-
gle word is received, SREN will be cleared and the
serial port will revert back to transmitting, since the
TXEN bit is still set. The DT line will immediately switch
from hi-impedance receive mode to transmit and start
driving. To avoid this, TXEN should be cleared.
In
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to TXREG.
This is because a data write to TXREG can result in an
immediate transfer of the data to the TSR (if the TSR is
empty). If the TSR was empty and TXREG was written
before writing the “new” TX9D, the “present” value of
TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner than doing these two events in the reverse
order.
Note:
Initialize the SPBRG register for the appropriate
baud rate (see Baud Rate Generator Section for
details).
Enable the synchronous master serial port by
setting the SYNC, SPEN, and CSRC bits.
Ensure that the CREN and SREN bits are clear
(these bits override transmission when set).
If interrupts are desired, then set the TXIE bit
(the GLINTD bit must be clear and the PEIE bit
must be set).
If 9-bit transmission is desired, then set the TX9
bit.
Start transmission by loading data to the
TXREG register.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Enable the transmission by setting TXEN.
order
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the
re-enabled.
to
proper
select
state
9-bit
when
transmission,
DS30264A-page 117
transmit
the
is
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