PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 248
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC17C756-16/L
Manufacturer Part Number
PIC17C756-16/L
Description
MICRO CTRL 16K MEMORY OTP 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756-16/L
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- PIC17C756CL PDF datasheet #5
- Current page: 248 of 321
- Download datasheet (3Mb)
FIGURE 20-19: MEMORY INTERFACE READ TIMING
TABLE 20-20: MEMORY INTERFACE READ REQUIREMENTS
DS30264A-page 248
Param.
No.
150
151
160
161
162
163
164
165
166
167
168
*
†
§
AD<15:0>
OSC1
Sym
TadV2alL
TalL2adI
TadZ2oeL AD15:AD0 hi-impedance to
ToeH2adD OE to AD15:AD0 driven
TadV2oeH Data in valid before OE
ToeH2adI
TalH
ToeL
TalH2alH
Tacc
Toe
ALE
WR
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25 C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
OE
'1'
Characteristic
AD15:AD0 (address) valid to
ALE
(address hold time)
OE
(data setup time)
(data hold time)
OE pulse width
ALE to ALE (cycle time)
Address access time
Output enable access time
(OE low to Data Valid)
ALE to address out invalid
OE to data in invalid
ALE pulse width
Q1
(address setup time)
Q2
164
Addr out
150
PIC17LCXXX
PIC17LCXXX
PIC17LCXXX
PIC17LCXXX
PIC17LCXXX
PIC17LCXXX
PIC17LCXXX
PIC17LCXXX
PIC17LCXXX
PIC17LCXXX
PIC17LCXXX
PIC17CXXX
PIC17CXXX
PIC17CXXX
PIC17CXXX
PIC17CXXX
PIC17CXXX
PIC17CXXX
PIC17CXXX
PIC17CXXX
PIC17CXXX
PIC17CXXX
Preliminary
167
Q3
151
160
168
0.5Tcy - 35 §
0.25Tcy - 10
0.25Tcy - 15
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min
35
166
5*
0*
—
—
—
—
—
—
—
—
0
165
Data in
162
Q4
0.25T
T
Typ†
TBD
TBD
CY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CY
§
163
§
0.75T
0.5T
Q1
1997 Microchip Technology Inc.
Max
TBD
TBD
CY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CY
- 45
- 30
161
Units Conditions
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Addr out
Q2
'1'
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