PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 309
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PIC17C756-16/L
Manufacturer Part Number
PIC17C756-16/L
Description
MICRO CTRL 16K MEMORY OTP 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756-16/L
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Regsters
Reset
Restart Condition Enabled bit, RSE.................................. 126
RETFIE ............................................................................. 207
RETLW ............................................................................. 207
RETURN ........................................................................... 208
RLCF................................................................................. 208
RLNCF .............................................................................. 209
RRCF ................................................................................ 209
RRNCF ............................................................................. 210
RSE................................................................................... 126
RX Pin Sampling Scheme................................................. 115
S
S........................................................................................ 124
SAE................................................................................... 126
Sampling ........................................................................... 115
Saving STATUS and WREG in RAM .................................. 38
SCK................................................................................... 127
SCL ................................................................................... 135
SDA................................................................................... 135
SDI .................................................................................... 127
SDO .................................................................................. 127
Serial Clock, SCK ............................................................. 127
Serial Clock, SCL .............................................................. 135
Serial Data Address, SDA................................................. 135
Serial Data In, SDI ............................................................ 127
Serial Data Out, SDO........................................................ 127
SETF ................................................................................. 210
SFR................................................................................... 184
SFR (Special Function Registers)....................................... 39
SFR As Source/Destination .............................................. 184
Signed Math.......................................................................... 9
Slave Select Synchronization ........................................... 130
Slave Select, SS ............................................................... 127
SLEEP ...................................................................... 180, 211
SMP .................................................................................. 124
Software Simulator (MPSIM) ............................................ 221
SPBRG ............................................................. 116, 120, 122
SPBRG1 ....................................................................... 25, 44
SPBRG2 ....................................................................... 25, 45
SPE................................................................................... 126
Special Features of the CPU ............................................ 177
Special Function Registers ................................... 39, 44, 184
Special Function Registers, File Map ......................... 43, 273
SPI
1997 Microchip Technology Inc.
TMR1 .......................................................................... 45
TMR2 .......................................................................... 45
TMR3H........................................................................ 45
TMR3L ........................................................................ 45
TXREG1...................................................................... 44
TXREG2...................................................................... 45
TXSTA1 ...................................................................... 44
TXSTA2 ...................................................................... 45
WREG................................................................... 35, 44
TMR0L ........................................................................ 44
Section ........................................................................ 21
Status Bits and Their Significance .............................. 23
Time-Out in Various Situations ................................... 23
Time-Out Sequence.................................................... 23
Summary..................................................................... 44
Master Mode ............................................................. 129
Serial Clock............................................................... 127
Serial Data In ............................................................ 127
Serial Data Out ......................................................... 127
Serial Peripheral Interface (SPI) ............................... 123
Preliminary
SPI Clock Edge Select, CKE ............................................ 124
SPI Data Input Sample Phase Select, SMP ..................... 124
SPI Master/Slave Connection........................................... 130
SPI Module
SS ..................................................................................... 127
SSP .................................................................................. 123
SSP I
SSP Module
SSP Overflow Detect bit, SSPOV..................................... 135
SSPADD ..............................................................................46
SSPBUF ............................................................. 46, 134, 135
SSPCON1 .......................................................... 46, 125, 134
SSPCON2 .................................................................. 46, 126
SSPEN ..................................................................... 125, 290
SSPIE ..................................................................................32
SSPIF ......................................................................... 34, 136
SSPM3:SSPM0 ........................................................ 125, 290
SSPOV ..................................................... 125, 135, 152, 290
SSPSTAT ........................................................... 46, 124, 134
Stack
Start bit (S) ....................................................................... 124
Start Condition Enabled bit, SAE...................................... 126
STKAV .......................................................................... 48, 50
Stop bit (P)........................................................................ 124
Stop Condition Enable bit ................................................. 126
SUBLW ............................................................................. 211
SUBWF............................................................................. 212
SUBWFB .......................................................................... 212
SWAPF ............................................................................. 213
Synchronous Master Mode............................................... 117
Synchronous Master Reception ....................................... 119
Synchronous Master Transmission .................................. 117
Synchronous Serial Port ................................................... 123
Synchronous Serial Port Enable bit, SSPEN............ 125, 290
Synchronous Serial Port Interrupt .......................................34
Synchronous Serial Port Interrupt Enable, SSPIE...............32
Synchronous Serial Port Mode Select bits,
SSPM3:SSPM0 ........................................................ 125, 290
Synchronous Slave Mode................................................. 121
T
T0CKI ..................................................................................35
Slave Select.............................................................. 127
SPI clock................................................................... 129
SPI Mode.................................................................. 127
Master/Slave Connection ......................................... 130
Slave Mode............................................................... 130
Slave Select Synchronization ................................... 130
Slave Synch Timnig.................................................. 131
Slave Timing with CKE = 0 ....................................... 132
Slave Timing with CKE = 1 ....................................... 133
Block Diagram (SPI Mode) ....................................... 128
SPI Mode.................................................................. 127
SSPADD........................................................... 134, 135
SSPBUF ........................................................... 129, 134
SSPCON1 ................................................................ 125
SSPCON2 ................................................................ 126
SSPSR ............................................................. 129, 135
SSPSTAT ......................................................... 124, 134
SSP I
SPI Master Mode...................................................... 129
SPI Master./Slave Connection.................................. 130
SPI Slave Mode........................................................ 130
SSPCON1 Register .................................................. 134
Operation.....................................................................50
Pointer .........................................................................50
Stack............................................................................39
2
C
2
C Operation ................................................... 134
DS30264A-page 309