PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 139
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PIC17C756-16/L
Manufacturer Part Number
PIC17C756-16/L
Description
MICRO CTRL 16K MEMORY OTP 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756-16/L
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- PIC17C756CL PDF datasheet #5
- Current page: 139 of 321
- Download datasheet (3Mb)
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the mas-
ter-receiver is latched on the rising edge of the ninth
SCL input pulse. If the SDA line was high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset and the
slave then monitors for another occurrence of the
START bit. If the SDA line was low (ACK), the transmit
data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Then the SCL pin
should be enabled by setting bit CKP.
FIGURE 15-19: GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
GCEN (SSPCON2<7>)
SDA
SCL
SSPIF (PIR2<7>)
SSPOV (SSPCON1<6>)
1997 Microchip Technology Inc.
BF (SSPSTAT<0>)
S
1
2
General Call Address
3
4
5
6
Preliminary
7
R/W = 0
8
ACK
Address is compared to General Call Address
after ACK, set interrupt
9
15.2.2
The addressing procedure for the I
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master.
which can address all devices. When this address is
used, all devices should, in theory, respond with an
acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I
consists of all 0’s with R/W = 0
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
= 1). Following a start-bit detect, 8-bits are shifted into
SSPSR and the address is compared against
SSPADD, and is also compared to the general call
address, fixed in hardware.
If the general call address matches, the SSPSR is
transfered to the SSPBUF, the BF flag is set (eigth bit),
and on the falling edge of the ninth bit (ACK bit) the
SSPIF interrupt is set.
When the interrupt is serviced. The source for the
interrupt can be checked by reading the contents of
the SSPBUF to determine if the address was device
specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the
UA bit is set (SSPSTAT<1>).
address is sampled when GCEN = 1 while the slave is
configured in 10-bit address mode, then the second
half of the address is not necessary, the UA bit will not
be set, and the slave will begin receiving data after the
acknowledge (Figure 15-19).
D7
1
D6
2
Cleared in software
SSPBUF is read
GENERAL CALL ADDRESS SUPPORT
The exception is the general call address
Receiving data
D5
3
D4
4
D3
5
D2
6
D1
7
D0
If the general call
8
2
DS30264A-page 139
C bus is such that
ACK
9
2
C protocol. It
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