PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 21
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC17C756-16/L
Manufacturer Part Number
PIC17C756-16/L
Description
MICRO CTRL 16K MEMORY OTP 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756-16/L
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- PIC17C756CL PDF datasheet #5
- Current page: 21 of 321
- Download datasheet (3Mb)
5.0
The PIC17CXXX differentiates between various kinds
of reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• Brown-out Reset
• WDT Reset (normal operation)
Some registers are not affected in any reset condition,
their status is unknown on POR and unchanged in any
other reset. Most other registers are forced to a “reset
state” on Power-on Reset (POR), Brown-out Reset
(BOR), on MCLR or WDT Reset and on MCLR reset
during SLEEP. A WDT Reset during SLEEP, is viewed
as the resumption of normal operation. The TO and PD
bits are set or cleared differently in different reset situ-
ations as indicated in Table 5-3. These bits are used in
software to determine the nature of the reset. See
Table 5-4 for a full description of reset states of all reg-
isters.
FIGURE 5-1:
1997 Microchip Technology Inc.
MCLR
OSC1
† This RC oscillator is shared with the WDT
V
DD
when not in a power-up sequence.
RESET
RC OSC†
OST/PWRT
On-chip
V
Module
Module
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
detect
WDT
DD
BOR
rise
OST
PWRT
10-bit Ripple counter
10-bit Ripple counter
Brown-out
Power_On_Reset
Reset
Time_Out
Reset
WDT
External
Reset
Preliminary
A simplified block diagram of the on-chip reset circuit is
shown in Figure 5-1.
Note:
Power_Up
(Enable the PWRT timer
only during Power_Up)
(Power_Up) + (Wake_Up) (XT + LF)
(Enable the OST if it is Power_Up or Wake_Up
from SLEEP and OSC type is XT or LF)
While the device is in a reset state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE and RE2/WR
pins as high outputs.
S
R
DS30264A-page 21
Q
Chip_Reset
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