PIC17C756-16I/L Microchip Technology, PIC17C756-16I/L Datasheet - Page 108

• Manufacturer Part Number: PIC17C756-16I/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

The USART can be configured as a full duplex asyn-
chronous system that can communicate with peripheral
devices such as CRT terminals and personal comput-
ers, or it can be configured as a half duplex synchro-
nous system that can communicate with peripheral
devices such as A/D or D/A integrated circuits, Serial
EEPROMs etc. The USART can be configured in the
following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
FIGURE 14-2: RCSTA1 REGISTER (ADDRESS: 13h, BANK 0)
DS30264A-page 108
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W - 0 R/W - 0 R/W - 0 R/W - 0
SPEN
SPEN: Serial Port Enable bit
1 = Configures TX/CK and RX/DT pins as serial port pins
0 = Serial port disabled
RX9: 9-bit Receive Select bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
This bit enables the reception of a single byte. After receiving the byte, this bit is automatically cleared.
Synchronous mode:
1 = Enable reception
0 = Disable reception
Note: This bit is ignored in synchronous slave reception.
Asynchronous mode:
Don’t care
CREN: Continuous Receive Enable bit
This bit enables the continuous reception of serial data.
Asynchronous mode:
1 = Enable continuous reception
0 = Disables continuous reception
Synchronous mode:
1 = Enables continuous reception until CREN is cleared (CREN overrides SREN)
0 = Disables continuous reception
Unimplemented: Read as '0'
FERR: Framing Error bit
1 = Framing error (Updated by reading RCREG)
0 = No framing error
OERR: Overrun Error bit
1 = Overrun (Cleared by clearing CREN)
0 = No overrun error
RX9D: 9th bit of receive data (can be the software calculated parity bit)
RX9
RCSTA2 REGISTER (ADDRESS: 13h, BANK 4)
SREN
CREN
U - 0
—
Preliminary
FERR
R - 0
The SPEN (RCSTA<7>) bit has to be set in order to
configure the I/O pins as the Serial Communication
Interface.
The USART module will control the direction of the
RX/DT and TX/CK pins, depending on the states of the
USART configuration bits in the RCSTA and TXSTA
registers. The bits that control I/O direction are:
• SPEN
• TXEN
• SREN
• CREN
• CSRC
OERR
R - 0
RX9D
R - x
bit 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
1997 Microchip Technology Inc.