PIC17C756-16I/L Microchip Technology, PIC17C756-16I/L Datasheet - Page 57

• Manufacturer Part Number: PIC17C756-16I/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

8.1
A table write operation to internal memory causes a
long write operation. The long write is necessary for
programming the internal EPROM. Instruction execu-
tion is halted while in a long write cycle. The long write
will be terminated by any enabled interrupt. To ensure
that the EPROM location has been well programmed,
a minimum programming time is required (see specifi-
cation #D114). Having only one interrupt enabled to
terminate the long write ensures that no unintentional
interrupts will prematurely terminate the long write.
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
TABLE 8-1:
RA0/INT, TMR0,
T0CKI
Peripheral
1997 Microchip Technology Inc.
Note 1: Programming requirements must be
Note 2: If the V
Disable all interrupt sources, except the source
to terminate EPROM program write.
Raise MCLR/V
age.
Clear the WDT.
Do the table write. The interrupt will terminate
the long write.
Verify the memory location (table read).
Interrupt
Source
Table Writes to Internal Memory
met. See timing specification in electrical
specifications for the desired device.
Violating these specifications (including
temperature) may result in EPROM
locations that are not fully programmed
and may lose their state over time.
table write is a 2 cycle write and the pro-
gram memory is unchanged.
INTERRUPT - TABLE WRITE INTERACTION
PP
PP
pin to the programming volt-
GLINTD
requirement is not met, the
0
0
1
1
0
0
1
1
Enable
Bit
1
1
0
1
1
1
0
1
Preliminary
Flag
Bit
1
0
x
1
1
0
x
1
8.1.1
An interrupt source or reset are the only events that
terminate a long write operation. Terminating the long
write from an interrupt source requires that the inter-
rupt enable and flag bits are set. The GLINTD bit only
enables the vectoring to the interrupt address.
If the T0CKI, RA0/INT, or TMR0 interrupt source is
used to terminate the long write; the interrupt flag, of
the highest priority enabled interrupt, will terminate the
long write and automatically be cleared.
If a peripheral interrupt source is used to terminate the
long write, the interrupt enable and flag bits must be
set. The interrupt flag will not be automatically cleared
upon the vectoring to the interrupt vector address.
The GLINTD bit determines whether the program will
branch to the interrupt vector when the long write is
terminated. If GLINTD is clear, the program will vector,
if GLINTD is set, the program will not vector to the
interrupt address.
Terminate long table write (to internal program
memory), branch to interrupt vector (branch clears
flag bit).
None
None
Terminate table write, do not branch to interrupt
vector (flag is automatically cleared).
Terminate table write, branch to interrupt vector.
None
None
Terminate table write, do not branch to interrupt
vector (flag remains set).
Note 1: If an interrupt is pending, the TABLWT is
Note 2: If the interrupt is not being used for the
TERMINATING LONG WRITES
aborted (an NOP is executed). The
highest priority pending interrupt, from
the T0CKI, RA0/INT, or TMR0 sources
that is enabled, has its flag cleared.
program write timing, the interrupt
should be disabled. This will ensure that
the interrupt is not lost, nor will it termi-
nate the long write prematurely.
Action
DS30264A-page 57