PIC17C756-16I/L Microchip Technology, PIC17C756-16I/L Datasheet - Page 314

• Manufacturer Part Number: PIC17C756-16I/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

Figure 16-3:
Figure 16-4:
Figure 16-5:
Figure 16-6:
Figure 16-7:
Figure 17-1:
Figure 17-2:
Figure 17-3:
Figure 17-4:
Figure 18-1:
Figure 18-2:
Figure 20-1:
Figure 20-2:
Figure 20-3:
Figure 20-4:
Figure 20-5:
Figure 20-6:
Figure 20-7:
Figure 20-8:
Figure 20-9:
Figure 20-10: SPI Master Mode Timing (CKE = 1) ......... 238
Figure 20-11: SPI Slave Mode Timing (CKE = 0) ........... 239
Figure 20-12: SPI Slave Mode Timing (CKE = 1) ........... 240
Figure 20-13: I
Figure 20-14: I
Figure 20-15: USART Synchronous Transmission
Figure 20-16: USART Synchronous Receive
Figure 20-17: A/D Conversion Timing ............................. 246
Figure 20-18: Memory Interface Write Timing................. 247
Figure 20-19: Memory Interface Read Timing ................ 248
Figure 21-1:
Figure 21-2:
Figure 21-3:
Figure 21-4:
Figure 21-5:
Figure 21-6:
Figure 21-7:
Figure 21-8:
Figure 21-9:
Figure 21-10: Maximum I
Figure 21-11: Typical I
Figure 21-12: Maximum I
Figure 21-13: WDT Timer Time-Out Period vs. V
Figure 21-14: I
Figure 21-15: I
Figure 21-16: I
Figure 21-17: I
Figure 21-18: V
Figure 21-19: V
DS30264A-page 314
A/D Block Diagram ................................... 169
Analog Input Model................................... 170
A/D Result Justification ............................. 173
A/D Transfer Function............................... 174
Flowchart of A/D Operation ...................... 175
Configuration Words ................................. 177
Watchdog Timer Block Diagram ............... 179
Wake-up From Sleep Through Interrupt ... 180
Typical In-Circuit Serial Programming
Connection................................................ 182
General Format for Instructions ................ 184
Q Cycle Activity......................................... 185
Parameter Measurement Information ....... 231
External Clock Timing ............................... 232
CLKOUT and I/O Timing........................... 233
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer, and Brown-out
Reset Timing............................................. 234
Timer0 External Clock Timings ................. 235
Timer1, Timer2, and Timer3 External
Clock Timings ........................................... 235
Capture Timings ....................................... 236
PWM Timings ........................................... 236
SPI Master Mode Timing (CKE = 0) ......... 237
(Master/Slave) Timing............................... 244
(Master/Slave) Timing............................... 244
Typical RC Oscillator Frequency vs.
Temperature ............................................. 249
Typical RC Oscillator Frequency vs. V
Typical RC Oscillator Frequency vs. V
Typical RC Oscillator Frequency vs. V
Transconductance (gm) of LF Oscillator
vs. V
Transconductance (gm) of XT Oscillator
vs. V
Typical I
Clock 25 C)............................................... 253
Maximum I
125 C to -40 C) ........................................ 253
Typical I
25 C.......................................................... 254
Disabled .................................................... 254
25 C.......................................................... 255
Enabled..................................................... 255
(TTL)
V
2
2
OH
OH
OL
OL
TH
IH
DD
C Bus Start/Stop Bits Timing.................. 241
C Bus Data Timing ................................. 242
, V
vs. V
vs. V
vs. V
vs. V
(Input Threshold Voltage) of I/O Pins
........................................................... 259
DD
DD
IL
VS
...................................................... 252
...................................................... 252
of I/O Pins (Schmitt Trigger)
DD
PD
PD
OL
OL
. V
OH
OH
DD
PD
PD
, V
, V
DD
vs. Frequency (External
vs. V
vs. V
, V
, V
DD
DD
............................................ 258
vs. Frequency (External Clock
vs. V
vs. V
DD
DD
DD
DD
= 3V ............................... 257
= 5V ............................... 258
= 3V .............................. 256
= 5V .............................. 257
DD
DD
Watchdog Disabled
Watchdog Enabled
Watchdog
Watchdog
DD
VS
....... 256
DD
DD
DD
.
. 250
. 250
. 251
Preliminary
Figure 21-20: V
Figure E-1:
Figure E-2:
Figure E-3:
Figure E-4:
Figure E-5:
Figure E-6:
Figure E-7:
Figure E-8:
Figure E-9:
Figure E-10:
Figure E-11:
Figure E-12:
Figure F-1:
Figure F-2:
Figure F-3:
Figure F-4:
Figure F-5:
Figure F-6:
Figure F-7:
Figure F-8:
Figure F-9:
Figure F-10:
Figure F-11:
Figure F-12:
Figure F-13:
Figure F-14:
Figure F-15:
Figure F-16:
Figure F-17:
Figure F-18:
Figure F-19:
Input (In XT and LF Modes) vs. V
Start and Stop Conditions ........................ 267
7-bit Address Format ................................ 268
I
Slave-receiver Acknowledge .................... 268
Data Transfer Wait State .......................... 268
Master-transmitter Sequence ................... 269
Master-receiver Sequence ....................... 269
Combined Format..................................... 269
Multi-master Arbitration
(Two Masters) .......................................... 270
Clock Synchronization .............................. 270
I
Specification ............................................. 271
I
PIC17C75X Register File Map ................. 273
ALUSTA Register (Address: 04h,
Unbanked) ................................................ 274
T0STA Register (Address: 05h,
Unbanked) ................................................ 275
CPUSTA Register (Address: 06h,
Unbanked) ................................................ 276
INTSTA Register (Address: 07h,
Unbanked) ................................................ 277
PIE1 Register (Address: 17h, Bank 1) ..... 278
PIE2 Register (Address: 11h, Bank 4) ..... 279
PIR1 Register (Address: 16h, Bank 1) ..... 280
PIR2 Register (Address: 10h, Bank 4) ..... 281
TXSTA1 Register (Address: 15h, Bank 0)
TXSTA2 Register (Address: 15h,
Bank 4) ..................................................... 282
RCSTA1 Register (Address: 13h,
Bank 0)
RCSTA2 Register (Address: 13h,
Bank 4) ..................................................... 283
TCON1 Register (Address: 16h,
Bank 3) ..................................................... 284
TCON2 Register (Address: 17h,
Bank 3) ..................................................... 285
TCON3 Register (Address: 16h,
Bank 7) ..................................................... 286
ADCON0 Register (Address: 14h,
Bank 5) ..................................................... 287
ADCON1 Register (Address 15h,
Bank 5) ..................................................... 288
SSPSTAT: Sync Serial Port Status
Register (Address: 13h, BANK 6)............. 289
SSPCON1: Sync Serial Port Control
Register (Address 11h, BANK 6).............. 290
SSPCON2: Sync Serial Port Control
Register2 (Address 12h, BANK 6)........... 291
2
2
2
TH
C 10-bit Address Format........................ 268
C Bus Start/Stop Bits Timing
C Bus Data Timing Specification .......... 272
(Input Threshold Voltage) of OSC1
1997 Microchip Technology Inc.
DD
....... 259