ATMEGA163-8PC Atmel, ATMEGA163-8PC Datasheet - Page 118

• Manufacturer Part Number: ATMEGA163-8PC
• Description: IC AVR MCU 16K A/D 8MHZ 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA163-8PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Port B As General Digital I/O
Alternate Functions Of
PORTB
118
ATmega163(L)
All eight bits in Port B are equal when used as digital I/O pins. PBn, General I/O pin: The
DDBn bit in the DDRB Register selects the direction of this pin, if DDBn is set (one), PBn
is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input
pin. If PORTBn is set (one) when the pin configured as an input pin, the MOS pull up
resistor is activated. To switch the pull up resistor off, the PORTBn has to be cleared
(zero), the pin has to be configured as an output pin, or the PUD bit has to be set. The
Port B pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
Table 46. DDBn Effects on Port B Pins
Note:
The alternate pin configuration is as follows:
• SCK – PORTB, Bit 7
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB7.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB7 bit. See the description of the SPI port for further details.
• MISO – PORTB, Bit 6
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is
enabled as a Master, this pin is configured as an input regardless of the setting of
DDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by
DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB6 bit. See the description of the SPI port for further details.
• MOSI – PORTB, Bit 5
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB5 bit. See the description of the SPI port for further details.
• SS – PORTB, Bit 4
SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured
as an input regardless of the setting of DDB4. As a slave, the SPI is activated when this
pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is
controlled by DDB4. When the pin is forced to be an input, the pull-up can still be con-
trolled by the PORTB4 bit. See the description of the SPI port for further details.
DDBn
0
0
0
1
1
1. n: 7,6…0, pin number.
PORTBn
0
1
1
0
1
PUD
x
1
0
x
x
Output
Output
Input
Input
Input
I/O
Pull Up
(1)
Yes
No
No
No
No
Comment
Tri-state (Hi-Z)
Tri-state (Hi-Z)
PBn will source current if ext. pulled low.
Push-pull Zero Output
Push-pull One Output
1142E–AVR–02/03