PIC18LF448-I/L Microchip Technology, PIC18LF448-I/L Datasheet - Page 278

• Manufacturer Part Number: PIC18LF448-I/L
• Description: IC PIC MCU FLASH 8KX16 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF448-I/L

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Controller Family/series: PIC18
• No. Of I/o's: 33
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

24.4
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro devices.
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The remain-
der of the memory is divided into four blocks on binary
boundaries.
FIGURE 24-3:
TABLE 24-3:
DS41159E-page 276
PIC18FXX8
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
File Name
Program Verification and
Code Protection
Unimplemented
Unimplemented
Unimplemented
(PIC18FX48)
16 Kbytes
Boot Block
Read ‘0’s
Read ‘0’s
Read ‘0’s
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
Block 0
Block 1
SUMMARY OF CODE PROTECTION REGISTERS
MEMORY SIZE/DEVICE
CODE-PROTECTED PROGRAM MEMORY FOR PIC18FXX8
WRTD
Bit 7
CPD
—
—
—
—
Unimplemented
(PIC18FX58)
Boot Block
32 Kbytes
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
EBTRB
WRTB
Bit 6
CPB
—
—
—
WRTC
Bit 5
—
—
—
—
—
000000h
0001FFh
000200h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
008000h
1FFFFFh
Address
Range
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-3 shows the program memory organization
for 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
Bit 4
—
—
—
—
—
—
(Unimplemented Memory Space)
EBTR3
WRT3
Bit 3
CP3
—
—
—
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Controlled By:
EBTR2
WRT2
Bit 2
CP2
© 2006 Microchip Technology Inc.
—
—
—
EBTR1
WRT1
Bit 1
CP1
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—