PIC18LF448-I/L Microchip Technology, PIC18LF448-I/L Datasheet - Page 300
![IC PIC MCU FLASH 8KX16 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC18LF448-I/L
Manufacturer Part Number
PIC18LF448-I/L
Description
IC PIC MCU FLASH 8KX16 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Specifications of PIC18LF448-I/L
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Controller Family/series
PIC18
No. Of I/o's
33
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
33
Number Of Timers
4 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163011
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF448-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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COMF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS41159E-page 298
PIC18FXX8
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
W
Q1
=
=
=
register ‘f’
Complement f
[ label ] COMF
0
d
a
N, Z
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
1
COMF
( f )
Read
0001
Q2
f
[0,1]
[0,1]
0x13
0x13
0xEC
255
dest
11da
REG, W
Process
Data
Q3
f [,d [,a]]
ffff
destination
Write to
Q4
ffff
CPFSEQ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC Address
W
REG
If REG
If REG
Q1
Q1
Q1
PC
PC
register ‘f’
operation
operation
operation
Compare f with W, Skip if f = W
[ label ] CPFSEQ
0
a
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
None
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
1
1(2)
Note:
HERE
NEQUAL
EQUAL
Read
0110
No
No
No
Q2
Q2
Q2
f
[0,1]
=
=
=
=
=
=
© 2006 Microchip Technology Inc.
255
3 cycles if skip and followed
by a 2-word instruction.
HERE
?
?
W;
Address (EQUAL)
W;
Address (NEQUAL)
001a
CPFSEQ REG
:
:
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
f [,a]
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
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