PIC18LF448-I/L Microchip Technology, PIC18LF448-I/L Datasheet - Page 315
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PIC18LF448-I/L
Manufacturer Part Number
PIC18LF448-I/L
Description
IC PIC MCU FLASH 8KX16 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Specifications of PIC18LF448-I/L
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Controller Family/series
PIC18
No. Of I/o's
33
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
33
Number Of Timers
4 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163011
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF448-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
After Interrupt
operation
Decode
No
PC = TOS
Q1
operation
operation
(TOS)
Return from subroutine. The stack is
Return from Subroutine
[ label ]
s
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged
None
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, Status and BSR. If ‘s’ = 0,
no update of these registers occurs
(default).
1
2
RETURN
0000
No
No
Q2
[0,1]
W,
PC,
RETURN [s]
BSR,
0000
operation
Process
Status,
Data
No
Q3
0001
from stack
operation
Pop PC
No
Q4
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
=
=
=
=
=
register ‘f’
Rotate Left f through Carry
[ label ]
0
d
a
(f<n>)
(f<7>)
(C)
C, N, Z
The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
1
1
RLCF
Read
0011
Q2
f
[0,1]
[0,1]
1110 0110
0
1110 0110
1100 1100
1
C
dest<0>
255
PIC18FXX8
dest<n + 1>,
C,
RLCF
01da
Process
Data
register f
Q3
REG, W
DS41159E-page 313
f [,d [,a]]
ffff
destination
Write to
Q4
ffff
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