ATMEGA169V-8MI Atmel, ATMEGA169V-8MI Datasheet - Page 150
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ATMEGA169V-8MI
Manufacturer Part Number
ATMEGA169V-8MI
Description
IC MCU AVR 16K 1.8V 1MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169V-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA169V-1MI
ATMEGA169V-1MI
ATMEGA169V-1MI
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SPI Status Register – SPSR
SPI Data Register – SPDR
150
ATmega169/V
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if
SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low
when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, the
SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing
the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register
with WCOL set, and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega169 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when
the SPI is in Master mode (see Table 69). This means that the minimum SCK period will
be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran-
teed to work at f
The SPI interface on the ATmega169 is also used for program memory and EEPROM
downloading or uploading. See page 281 for serial programming and verification.
The SPI Data Register is a read/write register used for data transfer between the Regis-
ter File and the SPI Shift Register. Writing to the register initiates data transmission.
Reading the register causes the Shift Register Receive buffer to be read.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
SPIF
MSB
R/W
R
7
0
7
X
osc
/4 or lower.
WCOL
R/W
R
6
0
6
X
R/W
R
5
–
0
5
X
R/W
R
X
4
–
0
4
R/W
R
X
3
–
0
3
R/W
R
X
2
–
0
2
R/W
R
X
1
–
0
1
SPI2X
LSB
R/W
R/W
X
0
0
0
2514P–AVR–07/06
Undefined
SPSR
SPDR
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