ATMEGA169V-8MI Atmel, ATMEGA169V-8MI Datasheet - Page 194
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATMEGA169V-8MI
Manufacturer Part Number
ATMEGA169V-8MI
Description
IC MCU AVR 16K 1.8V 1MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169V-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA169V-1MI
ATMEGA169V-1MI
ATMEGA169V-1MI
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Operation
194
ATmega169/V
Figure 83. Analog to Digital Converter Block Schematic
The ADC converts an analog input voltage to a 10-bit digital value through successive
approximation. The minimum value represents GND and the maximum value represents
the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 1.1V refer-
ence voltage may be connected to the AREF pin by writing to the REFSn bits in the
ADMUX Register. The internal voltage reference may thus be decoupled by an external
capacitor at the AREF pin to improve noise immunity.
The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the
ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected
as single ended inputs to the ADC. The ADC is enabled by setting the ADC Enable bit,
ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect
until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is
recommended to switch off the ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers,
ADCH and ADCL. By default, the result is presented right adjusted, but can optionally
be presented left adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to
read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content
of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access
AVCC
AREF
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
GND
REFERENCE
REFERENCE
INTERNAL
8-BIT DATA BUS
BANDGAP
INPUT
INPUT
POS.
NEG.
MUX
MUX
ADC MULTIPLEXER
SELECT (ADMUX)
MUX DECODER
+
-
SINGLE ENDED / DIFFERENTIAL SELECTION
DIFFERENTIAL
AMPLIFIER
10-BIT DAC
ADC CTRL. & STATUS
REGISTER (ADCSRA)
ADC CONVERSION
COMPLETE IRQ
PRESCALER
CONVERSION LOGIC
ADTS[2:0]
INTERRUPT
TRIGGER
SELECT
FLAGS
SAMPLE & HOLD
COMPARATOR
15
+
-
ADC DATA REGISTER
(ADCH/ADCL)
ADC MULTIPLEXER
OUTPUT
2514P–AVR–07/06
0
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