ATMEGA169V-8MI Atmel, ATMEGA169V-8MI Datasheet - Page 362
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ATMEGA169V-8MI
Manufacturer Part Number
ATMEGA169V-8MI
Description
IC MCU AVR 16K 1.8V 1MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169V-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA169V-1MI
ATMEGA169V-1MI
ATMEGA169V-1MI
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ATmega169/V
JTAG Interface and On-chip Debug System ................................. 226
IEEE 1149.1 (JTAG) Boundary-scan .............................................. 232
Boot Loader Support – Read-While-Write Self-Programming ..... 252
Memory Programming..................................................................... 266
Electrical Characteristics................................................................ 298
Mode of Operation ............................................................................................ 212
LCD Usage ....................................................................................................... 216
Overview........................................................................................................... 226
Test Access Port – TAP.................................................................................... 226
TAP Controller .................................................................................................. 228
Using the Boundary-scan Chain ....................................................................... 229
Using the On-chip Debug System .................................................................... 229
On-chip Debug Specific JTAG Instructions ...................................................... 230
On-chip Debug Related Register in I/O Memory .............................................. 231
Using the JTAG Programming Capabilities ...................................................... 231
Bibliography ...................................................................................................... 231
Features............................................................................................................ 232
System Overview.............................................................................................. 232
Data Registers .................................................................................................. 232
Boundary-scan Specific JTAG Instructions ...................................................... 234
Boundary-scan Related Register in I/O Memory .............................................. 235
Boundary-scan Chain ....................................................................................... 236
ATmega169 Boundary-scan Order................................................................... 246
Boundary-scan Description Language Files ..................................................... 251
Boot Loader Features ....................................................................................... 252
Application and Boot Loader Flash Sections .................................................... 252
Read-While-Write and No Read-While-Write Flash Sections........................... 252
Boot Loader Lock Bits....................................................................................... 255
Entering the Boot Loader Program ................................................................... 256
Addressing the Flash During Self-Programming .............................................. 258
Self-Programming the Flash ............................................................................. 259
Program And Data Memory Lock Bits .............................................................. 266
Fuse Bits........................................................................................................... 267
Signature Bytes ................................................................................................ 269
Calibration Byte ................................................................................................ 269
Page Size ......................................................................................................... 269
Parallel Programming Parameters, Pin Mapping, and Commands .................. 269
Serial Programming Pin Mapping ..................................................................... 272
Parallel Programming ....................................................................................... 273
Serial Downloading........................................................................................... 281
Programming via the JTAG Interface ............................................................... 285
2514P–AVR–07/06
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