ST92F250CV2QB STMicroelectronics, ST92F250CV2QB Datasheet - Page 256

IC MCU 256K FLASH 100-PQFP

ST92F250CV2QB

Manufacturer Part Number
ST92F250CV2QB
Description
IC MCU 256K FLASH 100-PQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet

Specifications of ST92F250CV2QB

Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-QFP
Processor Series
ST92F25x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
5 x 16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit x 10 bit
Case
QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2139

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST92F250CV2QB
Manufacturer:
HKE
Quantity:
30 000
Part Number:
ST92F250CV2QB
Manufacturer:
ST
0
SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.7.4.4 Write Collision Error
A write collision occurs when the software tries to
write to the SPDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted and
the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
In Slave mode
When the CPHA bit is set:
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
SPDR register and output the MSBit on to the ex-
ternal MISO pin of the slave device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
Figure 124. Clearing the WCOL bit (Write Collision Flag) Software Sequence
256/429
9
1
2
st
nd
Step
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Clearing sequence before SPIF = 1 (during a data byte transfer)
Step
1
2
st
nd
Step
Step
Read SPDR
Read SPSR
THEN
SPIF =0
WCOL=0
Read SPDR
Read SPSR
THEN
WCOL=0
When the CPHA bit is reset:
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the SPDR register after
its SS pin has been pulled low.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the SPDR register without generating a write
collision.
In Master mode
Collision in the master device is defined as a write
of the SPDR register while the internal serial clock
(SCK) is in the process of transfer.
The SS pin signal must be always high on the
master device.
WCOL Bit
The WCOL bit in the SPSR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see
Note: Writing in SPDR register
instead of reading in it do not re-
set WCOL bit
Figure
124).

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