ST92F250CV2QB STMicroelectronics, ST92F250CV2QB Datasheet - Page 263

• Manufacturer Part Number: ST92F250CV2QB
• Description: IC MCU 256K FLASH 100-PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F250CV2QB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-QFP
• Processor Series: ST92F25x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2139

I
Figure 126. I
10.8.3 Functional Description
Refer to the I2CCR, I2CSR1 and I2CSR2 registers
in
The I
between the ST9 microcontroller and the I
protocol. In addition to receiving and transmitting
data, the interface converts data from serial to
parallel format and vice versa using an interrupt or
polled handshake.
It operates in Multimaster/slave I
lection of the operating mode is made by software.
The I
data pin (SDA) and a clock pin (SCL) which must
be configured as open drain when the I
enabled by programming the I/O port bits and the
PE bit in the I2CCR register. In this case, the value
of the external pull-up resistance used depends on
the application.
When the I
ports revert to being standard I/O port pins.
2
C BUS INTERFACE (Cont’d)
Section
2
2
C interface is connected to the I
C interface works as an I/O interface
SCL
SDA
10.8.7. for the bit definitions.
2
C cell is disabled, the SDA and SCL
2
C Interface Block Diagram
DMA
CONTROL
CONTROL
CLOCK
DATA
CONTROL SIGNALS
2
C mode. The se-
2
C bus by a
2
C cell is
2
C bus
LOGIC AND INTERRUPT/DMA REGISTERS
CLOCK CONTROL REGISTER
OWN ADDRESS REGISTER 2
OWN ADDRESS REGISTER 1
GENERAL CALL ADDRESS
DATA SHIFT REGISTER
STATUS REGISTER 1
STATUS REGISTER 2
CONTROL REGISTER
DATA BUS
The I
Six of them are used for initialization:
– Own Address Registers I2COAR1, I2COAR2
– General Call Address Register I2CADR
– Clock Control Registers I2CCCR, I2CECCR
– Control register I2CCR
The following four registers are used during data
transmission/reception:
– Data Register I2CDR
– Control Register I2CCR
– Status Register 1 I2CSR1
– Status Register 2 I2CSR2
DATA REGISTER
COMPARATOR
2
C interface has sixteen internal registers.
INTERRUPT
I2C BUS INTERFACE
VR02119A
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