MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 27

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Freescale Semiconductor, Inc.
List of Figures
Figure
Title
Page
20-16 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
20-17 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . . 318
20-18 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . . 319
20-19 Port F I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
20-20 Port G Data Register (PTG) . . . . . . . . . . . . . . . . . . . . . . . . . . 320
20-21 Data Direction Register G (DDRG). . . . . . . . . . . . . . . . . . . . . 321
20-22 Port G I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
20-23 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . . 323
20-24 Data Direction Register H (DDRH) . . . . . . . . . . . . . . . . . . . . . 324
20-25 Port H I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
21-1 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
21-2 BDLC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 331
21-3 BDLC Operating Modes State Diagram . . . . . . . . . . . . . . . . . 332
21-4 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
21-5 BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . . . .335
21-6 J1850 Bus Message Format (VPW) . . . . . . . . . . . . . . . . . . . . 338
21-7 J1850 VPW Symbols with Nominal Symbol Times. . . . . . . . .343
21-8 J1850 VPW Received Passive Symbol Times . . . . . . . . . . . . 346
21-9 J1850 VPW Received Passive
EOF and IFS Symbol Times . . . . . . . . . . . . . . . . . . . . . . .347
21-10 J1850 VPW Received Active Symbol Times . . . . . . . . . . . . . 348
21-11 J1850 VPW Received BREAK Symbol Times . . . . . . . . . . . . 349
21-12 J1850 VPW Bitwise Arbitrations . . . . . . . . . . . . . . . . . . . . . . .350
21-13 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
21-14 BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . . . .352
21-15 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
21-16 BDLC Analog and Roundtrip Delay Register (BARD) . . . . . . 358
21-17 BDLC Control Register 1 (BCR1) . . . . . . . . . . . . . . . . . . . . . . 359
21-18 BDLC Control Register 2 (BCR2) . . . . . . . . . . . . . . . . . . . . . . 362
21-19 Types of In-Frame Response (IFR) . . . . . . . . . . . . . . . . . . . . 366
21-20 BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . . . . 370
21-21 BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 372
22-1 TIMA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
22-2 TIMA I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 378
MC68HC908AS60 — Rev. 1.0
Technical Data
List of Figures
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