MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 362

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Byte Data Link Controller-Digital (BDLC-D)
21.7.3 BDLC Control Register 2
Technical Data
Address:
This register controls transmitter operations of the BDLC. It is
recommended that BSET and BCLR instructions be used to manipulate
data in this register to ensure that the register’s content does not change
inadvertently.
ALOOP — Analog Loopback Mode Bit
Reset:
Read:
Write:
This bit determines whether the J1850 bus will be driven by the
analog physical interface’s final drive stage. The programmer can use
this bit to reset the BDLC state machine to a known state after the
off-chip analog transceiver is placed in loopback mode. When the
user clears ALOOP, to indicate that the off-chip analog transceiver is
no longer in loopback mode, the BDLC waits for an EOF symbol
before attempting to transmit. Most transceivers have the ALOOP
feature available.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Input to the analog physical interface’s final drive stage is
0 = The J1850 bus will be driven by the BDLC. After the bit is
Byte Data Link Controller-Digital (BDLC-D)
ALOOP
$003D
Bit 7
looped back to the BDLC receiver. The J1850 bus is not driven.
cleared, the BDLC requires the bus to be idle for a minimum of
end-of-frame symbol time (t
a minimum of inter-frame symbol time (t
transmission. See
Timings.
1
Figure 21-18. BDLC Control Register 2 (BCR2)
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DLOOP
6
1
RX4XE
5
0
24.15 BDLC Receiver VPW Symbol
NBFS
4
0
TRV4
TEOD
) before message reception or
3
0
MC68HC908AS60 — Rev. 1.0
TSIFR
TRV6
2
0
) before message
TMIFR1
1
0
TMIFR0
Bit 0
0