MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 69

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MC68HC908AS60 — Rev. 1.0
NOTE:
ordinary read mode except that a built-in counter stretches the data
access for an additional eight cycles to allow sensing of the lower cell
current. Margin read mode imposes a more stringent read condition on
the bitcell to ensure the bitcell is programmed with enough margin for
long-term data retention. During these eight cycles, the COP counter
continues to run. The user must account for these extra cycles within
COP feed loops. A margin read cycle can only follow a page
programming operation.
To program and margin read the FLASH memory, use this step-by-step
algorithm. See
of the times used in this algorithm.
While these operations must be performed in the order shown, other
unrelated operations may occur between the steps.
10. Clear the PGM bit.
11. Wait for a time, t
12. Read back data in margin read mode. This is done in eight
13. Clear the MARGIN bit.
1. Set the PGM bit. This configures the memory for program
2. Read from the block protect register (FLBPR1).
3. Write data to the eight bytes of the page being programmed. This
4. Set the HVEN bit.
5. Wait for a time, t
6. Clear the HVEN bit.
7. Wait for a time, t
8. Set the MARGIN bit.
9. Wait for a time, t
Freescale Semiconductor, Inc.
For More Information On This Product,
operation and enables the latching of address and data for
programming.
requires eight separate write operations.
separate read operations which are each stretched by eight
cycles.
Go to: www.freescale.com
24.13 Memory Characteristics
FLASH-1 Memory
PROG
HVTV
VTP
HVD
.
.
.
.
FLASH Program/Margin Read Operation
for a detailed description
FLASH-1 Memory
Technical Data