MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 340

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Byte Data Link Controller-Digital (BDLC-D)
21.5.2.6 End-of-Frame Symbol (EOF)
21.5.2.7 Inter-Frame Separation Symbol (IFS)
Technical Data
This symbol is a long 280- s passive period on the J1850 bus and is
longer than an end-of-data (EOD) symbol, which signifies the end of a
message. Since an EOF symbol is longer than a 200- s EOD symbol, if
no response is transmitted after an EOD symbol, it becomes an EOF,
and the message is assumed to be completed. The EOF flag is set upon
receiving the EOF symbol.
The IFS symbol is a 20- s passive period on the J1850 bus which allows
proper synchronization between nodes during continuous message
transmission. The IFS symbol is transmitted by a node after the
completion of the end-of-frame (EOF) period and, therefore, is seen as
a 300- s passive period.
When the last byte of a message has been transmitted onto the J1850
bus and the EOF symbol time has expired, all nodes then must wait for
the IFS symbol time to expire before transmitting a start-of-frame (SOF)
symbol, marking the beginning of another message.
However, if the BDLC is waiting for the IFS period to expire before
beginning a transmission and a rising edge is detected before the IFS
time has expired, it will synchronize internally to that edge.
A rising edge may occur during the IFS period because of varying clock
tolerances and loading of the J1850 bus, causing different nodes to
observe the completion of the IFS period at different times. To allow for
individual clock tolerances, receivers must synchronize to any SOF
occurring during an IFS period.
Freescale Semiconductor, Inc.
For More Information On This Product,
Byte Data Link Controller-Digital (BDLC-D)
Go to: www.freescale.com
MC68HC908AS60 — Rev. 1.0